Department of Computer Science and Engineering
University of California, San Diego
"Conservation Cores: Architectures for a Future of Dark Silicon"
Concerns over leakage currents have moved us out of the classical CMOS scaling regime. Although the number of available transistors continues to rise, their switching power no longer declines commensurately. Meanwhile, power budgets remain fixed due to practical limitations on cooling or battery life. Thus, we now face a Utilization Wall: For a given power and area budget, an exponentially decreasing fraction of the available transistors can be simultaneously switched at full frequency, giving rise to the phenomenon of dark silicon. My recent work has focused on a class of automatically-generated energy-reducing coprocessors, called conservation cores (C-Cores), as a means of surmounting the Utilization Wall’s most pressing challenges. We have constructed C-Cores that improve EDP by more than 10x over an efficient, in-order core. In this talk, I will characterize the Utilization Wall, discuss the origins and implications of the growing phenomenon of dark silicon, and show how we can design new, aggressively heterogeneous architectures to manage and exploit the growth of dark silicon.