I work on making multiprocessors easier to program by leveraging changes in both computer architectures and parallel programming models.

I am looking for new PhD students interested in systems and computer architecture. If you are interested in these topics please apply to our PhD program and drop me an email as well.

Teaching

In Fall 2023 I'm teaching CIS 6010: GPGPU Programming and Architecture.

Students

I'm lucky to be working with the following great students:

• Kelly Shiptoski (PhD)
• Yuxuan Zhang (PhD)

Former students

• Omar Navarro Leija (PhD 2022. First employment: Bolt Labs)
• Gautam Mohan (Master's 2020. First employment: Amazon)
• Yuanfeng Peng (PhD 2019). First employment: Google
• Nicholas Renner (Master's 2019, now a PhD student at NYU)
• Nimit Singhania (PhD 2018, co-advised with Rajeev Alur). First employment: Google
• Christian DeLozier (PhD 2018). First employment: Assistant Professor at United States Naval Academy
• Kavya Lakshminarayanan (Master's 2018) First employment: Microsoft
• Richard Zang (Master's 2018) First employment: Microsoft
• Sana Kamboj (Master's 2017) First employment: Qualcomm
• Ariel Eizenberg (Master's 2016) First employment: Government of Israel
• Brooke Fugate (Master's 2015, co-advised with André DeHon)
• Liang Luo (Master's 2015, then a PhD student at the University of Washington)
• Akshitha Sriraman (Master's 2015, then a PhD student at the University of Michigan)

Recent Publications full list

Many of the paper links below use the ACM's Author-izer service, which tracks download statistics and provides a small kickback to various ACM Special Interest Groups for each download.

• OCOLOS: Online COde Layout OptimizationSOCOLOS: Online COde Layout OptimizationS
  Yuxuan Zhang, Tanvir Ahmed Khan, Gilles Pokam, Baris Kasikci, Heiner Litz and Joseph Devietti
  ACM IEEE International Symposium on Microarchitecture (MICRO '22), October 2022
  [abstract]
  Selected for IEEE Micro Top Picks 2023

  The processor front-end has become an increasingly important bottleneck in recent years due to growing application code footprints, particularly in data centers. First-level instruction caches and branch prediction engines have not been able to keep up with this code growth, leading to more front-end stalls and lower Instructions Per Cycle (IPC). Profile-guided optimizations performed by compilers represent a promising approach, as they rearrange code to maximize instruction cache locality and branch prediction efficiency along a relatively small number of hot code paths. However, these optimizations require continuous profiling and rebuilding of applications to ensure that the code layout matches the collected profiles. If an application’s code is frequently updated, it becomes challenging to map profiling data from a previous version onto the latest version, leading to ignored profiling data and missed optimization opportunities.

  In this paper, we propose OCOLOS, the first online code layout optimization system for unmodified applications written in unmanaged languages. OCOLOS allows profile-guided optimization to be performed on a running process, instead of being performed offline and requiring the application to be re-launched. By running online, profile data is always relevant to the current execution and always maps perfectly to the running code. OCOLOS demonstrates how to achieve robust online code replacement in complex multithreaded applications like MySQL and MongoDB, without requiring any application changes. Our experiments show that OCOLOS can accelerate MySQL by up to 1.41x, the Verilator hardware simulator by up to 2.20x, and a build of the Clang compiler by up to 1.14x.

• Twig: Profile-Guided BTB Prefetching for Data Center ApplicationsTwig: Profile-Guided BTB Prefetching for Data Center Applications
  Tanvir Ahmed Khan, Nathan Brown, Akshitha Sriraman, Niranjan K Soundararajan, Rakesh Kumar, Joseph Devietti, Sreenivas Subramoney, Gilles Pokam, Heiner Litz and Baris Kasikci
  ACM IEEE International Symposium on Microarchitecture (MICRO '21), October 2021
  [abstract][paper]

  Modern data center applications have deep software stacks, with instruction footprints that are orders of magnitude larger than typical instruction cache (I-cache) sizes. To efficiently prefetch instructions into the I-cache despite large application footprints, modern server-class processors implement a decoupled frontend with Fetch Directed Instruction Prefetching (FDIP). In this work, we first characterize the limitations of a decoupled frontend processor with FDIP and find that FDIP suffers from significant Branch Target Buffer (BTB) misses. We also find that existing techniques (e.g., stream prefetchers and predecoders) are unable to mitigate these misses, as they rely on an incomplete understanding of a program’s branching behavior.

  To address the shortcomings of existing BTB prefetching techniques, we propose Twig, a novel profile-guided BTB prefetching mechanism. Twig analyzes a production binary’s execution profile to identify critical BTB misses and inject BTB prefetch instructions into code. Additionally, Twig coalesces multiple non-contiguous BTB prefetches to improve the BTB’s locality. Twig exposes these techniques via new BTB prefetch instructions. Since Twig prefetches BTB entries without modifying the underlying BTB organization, it is easy to adopt in modern processors. We study Twig’s behavior across nine widely-used data center applications, and demonstrate that it achieves an average 20.86% (up to 145%) performance speedup over a baseline 8K-entry BTB, outperforming the state-of-the-art BTB prefetch mechanism by 19.82% (on average).