Testing your processor is accomplished by comparing its output to the simulator's output. "Output" in this case means comparing the PC, the current instruction, the data memory signals and the data going into the register file on every cycle. The output generated by a particular run of a program is known as a trace. Your single-cycle processor should produce the same exact trace as the simulator for a given program.
The testbench itself. Note that the .tf file extension causes Xilinx to automatically recognize the file as a Verilog test fixture. You'll also need two of the files from the zip archive available in the hardware tutorial.
You'll also need the most recent version of PennSim.
You can generate a trace from the simulator by using the simulator's aptly-named trace command.
You will need to modify your processor to accept your newly-created memory image and trace file. This requires editing the value of the MEMORY_IMAGE_FILE macro at the top of the memory module bram.v. This memory module is used both for simulation and for synthesis, so if you change it in one place it will affect the other.
You also need to edit which trace file is used by the testbench. This line is clearly marked in test_sc_datapath.v with a comment.
Running the testbench in ModelSim will then load the memory with your program, and then let your processor begin executing. On every cycle, the simulator's trace output is compared with the real signals coming out of your processor, and errors are printed accordingly. No news is good news!
Start small - a big program (such as breakout or snake) isn't the ideal first test case. Write some code to test just one kind of instruction at a time (e.g. ALU operations, loads, branches) and build up as you go. A larger program may also not actually test every instruction; for example, our reference implementation of breakout doesn't use any JSRR instructions, for example.