Running Your Non-Pipelined Processor On The Board (Lab 2)

CSE 372 (Spring 2007): Digital Systems Organization and Design Lab

Overview

This tutorial will demonstrate how to implement your design in Xilinx and download it to the FPGA for hardware testing. It will also cover using the debugging features of the FPGA. This testing should only be done after the processor has been extensively tested in the simulator, as ModelSim gives more useful information when errors are encountered.

Note: Implementing your design takes approximately 20 minutes if running from the local harddrive, and upwards of an hour if running over the network.

Requirements

The zip file containing the top level module and all other necessary files.

Instructions

Implementing and Downloading Your Design

Unpack the zip file into the folder where your project is located. Verify that the instantiation of sc_datapath on line 174 of p37x_processor.v matches your declaration.
Enable filtering of the warning messages that our provided code generates. The warnings from your code will still be displayed as usual. There is a file called filter.filter that's part of the provided archive; place this filter file in your project directory. In Xilinx ISE, select the Edit menu and then Messages... A dialog box will pop-up asking if you want to enable message filtering; select Yes.
Generate a hex file for your memory input image. Refer to the software testing tutorial to do this. Make sure that the dumped hex file resides in your project directory and that the macro definition of MEMORY_IMAGE_FILE in bram.v on line 2 matches your dumped file name. If you do not do this, you'll get the following error during implementation: FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.16
Double click on configure device (make sure that p37x_processor is set as the top level module) and give it about 20 minutes to complete.
When iMPACT opens, select the bit file and program the board just as was done in the previous labs.

Test Programs

In addition to your own test programs, we're giving you a hex dump file that contains three games: tetris, breakout, and snake. As well as a nifty program chooser writen by TA Andrew Lagattuta. To choose a program, use the "s" key to move down, the "w" key to move up, and the "d" key to select the highlighted item. The compressed hex dump is: p37os.hex.zip. You'll use this during the demo of your design to us.

If you want to just test out breakout, we also have a compressed hex dump for just that: breakout.hex.zip.

Running Your Program on the Board

Immediately after download, the processor begins executing its instructions.

The clock can be set to either automatic or manual control. This is done with switch 1 (the leftmost) of the on-board (not extension board) switches. When the switch is down, the processor is in manual control. In this setting, use the down button on the board to advance the clock one cycle (this button is actually controlling the global write enable signal sent into all of your modules). When switch 1 is up, the clock will advance automatically.

The right button on the board resets the processors registers and memory, and sets the program counter back to its initial state. This button does not reset video memory, to do this you must reprogram the device.

On-board switches 2, 3, and 4 are used in conjunction with the seven segment display on the external board to display debugging information about the processor. In the following table, a 0 means down and a 1 means up, as we've inverted the switches.

sw2	sw3	sw4	information displayed
0	0	0	7-segment data (memory of address 0xFE04)
0	0	1	Current PC value
0	1	0	Current Instruction
0	1	1	Regfile write data
1	0	0	{reset,0,regfile we,dmem we}
1	0	1	dmem address
1	1	0	dmem data out
1	1	1	dmem data in

Xilinx Trouble Shooting Hints

A few hints on what to do if Xilinx is being flaky:

If something "strange" happens, the best bet is to create a brand new project, re-import the verilog files and then retry what you were trying to do. For some reason this fixes many mysterious problems.
Be sure you specified the correct FPGA when you set up the project. If you selected the wrong FPGA, the design may fail to place&route because it isn't big enough (for example, doesn't have enough block RAMs).
Sometimes it seems strange non-ASCII characters get inserted into a Verilog file. This makes Xilinx seemly randomly skip sections of the Verilog file. If you're seeing some strange errors, copy the Verilog file and then paste it into Notepad. If you see any strange characters, delete them and then copy&paste it back into Xilinx.

For the most part, once the bit file has been generated correctly, most designs have worked well on the boards. It seems the only glitches have been in the steps to actually generate the bits files.

Addenda

[March 15] - The most recent version of PennSim (version 1.3.1) includes suport to read in .hex files using the "load" command. It will also try to load a corresponding .sym file, so I've added the .sym file to p37os.hex.zip.
[March 13] - Added the hex file with three games in it: p37os.hex.zip