CSE 372 (Spring 2007): Digital Systems Organization and Design Lab

Instructor:Prof. Milo Martin
Office hours:Wed 3:00-4:30 (or by appointment)
Lecture:Friday 3:00-4:30 in Towne 321
TAs:Tony Curnes, Peter Hornyack, Andrew Lagatutta, Armand O'Donnell, Zheng Yang
Admin:Cheryl Hickey (cheryl@central.cis) - 502 Levine Hall
Board:CSE372 PHPbb discussion board

This course is the lab component of CSE371.


Office Hours

KLab schedule

The TAs are in the KLab at the following times:


Lecture Notes


Friday, Jan 12: Introduction
Friday, Jan 19: In-lab meeting for Lab 0
Wed., Jan 24: Verilog
Friday, Jan 26: (swapped with CSE371)
Friday, Feb 2: Verilog (continued)
Friday, Feb 9: FPGAs
Friday, Feb 16: Design and P37x Processor
Friday, Feb 23: (CSE371 midterm)
Friday, Mar 2: no class (spring break)
Friday, Mar 19: no class (spring break)
Friday, Mar 16: Pipelined P37x Processor
Friday, Mar 23: Synthesis
Friday, Mar 30: no class
Friday, Apr 6: no class
Friday, Apr 13: no class
Wednesday, Apr 18: Wrapup & evaluations

Additional Reading Materials and Resources

CSE372 tutorials:

Xilinx documentation:

On-line Verilog references:

In addition, the textbook for CSE371 (Patterson and Hennessy's Computer Organization and Design) has a Verilog tutorial on the included CD. Look for it under "tutorials" and "Verilog".

There is no additional textbook required for CSE372. However, we'll be using the Verilog hardware description language (HDL), so you may wish to obtain or consult one of the following books on Verilog:

Course Syllabus

Course Description

This course is the lab component companion of CSE371. The focus of CSE372 is hands-on digitial logic design. The description from the course catalog:

Laboratory for CSE 371. In this laboratory section, students gain experience
with digital design techniques by designing and implementing actual ciruits
using Verilog HDL and FPGAs. Five assignments culminate in the design and
simulation of a complete 16-bit integer pipelined CPU.


CSE240 is an absolute prerequisite for this course. In addition, CSE372 is a co-requisite (that is, it must be taking CSE372 in parallel).


Grading breakdown for the course is as follows:

  • Labs: 80% - The course project consists of six labs. The initial labs will be individual labs, the later labs will be done in groups of three.
  • Exams: 20% - There will be one exam to test the material covered in the CSE372 lectures.

Academic Misconduct

Academic misconduct such as cheating will not be tolerated. The work you submit in this class is expected to be your own. If you submit work that has in part or in whole been copied from some published or unpublished source (including current or former students), or that has been prepared by someone other than you, or that in any way misrepresents somebody else's work as your own, you will face severe discipline by the university. (Adapted from text appearing at the Office of Student Conduct page.)

Any detected cases of cheating will be pursued. Penalties can include: receiving a zero on the assignment (the minimum penalty), failing the course, having a note placed in your permanent academic record, suspension, and ultimately expulsion.

See Penn's Code of Academic Integrity for more information.