Announcements

• [Mar 27] - Lab 4: Pipelined processor is now available
• [Mar 17] - Lab 3: Non-pipelined processor is now available
• [Feb 12] - Lab 2: Register file is now available
• [Jan 30] - Lab 1: Combinational logic and ALUs and the ModelSim Simulation Tutorial are now available
• [Jan 26] - Updated instructions for mapping your eniac drive
• [Jan 18] - Lab 0: Getting started and the Xilinx Verilog Tutorial are now available

Office Hours

The TAs are in the KLab at the following times:

• Monday: 1pm-3pm (Zheng), 4:30-7pm (Josh)
• Tuesday: 3pm-5pm (Zheng)
• Wednesday: 3pm-5pm (Zheng)
• Thursday: 3pm-5pm (Zheng), 4:30-7pm (Josh)
• Friday: 2pm-7pm (Joe and Andrew), 3:30pm-5pm (Zheng)

Labs

• Lab 0: Getting started
• Lab 1: Combinational logic and ALUs
• Lab 2: Register file
• Lab 3: Non-pipelined processor
• Lab 4: Pipelined processor

Lecture Notes

• Unit 0 - Introduction
• Unit 1 - Verilog
• Unit 2 - FPGAs
• Unit 3 - "Design" - no formal lecture notes
• Unit 4 - P37X Processor
• Unit 5 - Synthesis
• Unit 6 - P37X Pipelined
• Unit 7 - Pipelining Hints and Wrapup

Schedule

• Monday, Jan 9th: Introduction
• Monday, Jan 16th: no class (MLK day)
• Wednesday, Jan 18th: In-lab meeting for Lab 0
• Monday, Jan 23rd: Verilog
• Monday, Jan 30th: Verilog (continued)
• Monday, Feb 6th: FPGAs
• Monday, Feb 13th: no class
• Monday, Feb 20th: "Design"
• Monday, Feb 27th: [Review for CSE371]
• Monday, Mar 6th: no class (Spring break)
• Monday, Mar 13th: P37X Processor
• Monday, Mar 20th: Synthesis
• Monday, Mar 27th: P37X Pipelined
• Monday, Apr 3rd: no class
• Monday, Apr 10th: Yale Patt lecture
• Monday, Apr 17th: Wrapup & evaluations

Additional Reading Materials and Resources

CSE372 tutorials:

• Instructions for mapping your eniac drive
• Xilinx Verilog Tutorial
• ModelSim Simulation Tutorial

Xilinx documentation:

• Xilinx Synthesis and Verification Design Guide - information on what synthesis results to expect given HDL input code.
• Xilinx Synthesis Technology (XST) User Guide - information about Xilinx primitives and Verilog examples that will synthesis to specific structures.
• Xilinx Constraints Guide - information about various synthesis parameters and tuning.

On-line Verilog references:

• The Elements of Logic Design Style by Shing Kong, 2001.
• On-line Verilog HDL Quick Reference Guide
• Useful Verilog links

In addition, the textbook for CSE371 (Patterson and Hennessy's Computer Organization and Design) has a Verilog tutorial on the included CD. Look for it under "tutorials" and "Verilog".

There is no additional textbook required for CSE372. However, we'll be using the Verilog hardware description language (HDL), so you may wish to obtain or consult one of the following books on Verilog:

• Verilog HDL Synthesis: A Practical Primer by J. Bhasker, 1998. A approximately 200 page overview of a synthesizeable subset of Verilog.
• Advanced Digital Design with the Verilog HDL by Michael Ciletti, 2003. Verilog plus lots of digital logic design (almost 1000 pages).
• HDL Programming Fundamentals: VHDL and Verilog by Nazeih Botros, 2006. A good interleaved description of Verilog and VHDL; it has approximately 500 pages, but as both VHDL and Verilog are covered, it doesn't cover that much more than Bhasker.

Course Syllabus

Laboratory for CSE 371. In this laboratory section, students gain experience
with digital design techniques by designing and implementing actual ciruits
using Verilog HDL and FPGAs. Five assignments culminate in the design and
simulation of a complete 16-bit integer pipelined CPU.