# Homework 2a - CIS501 Fall 2012

Instructor: Prof. Milo Martin Wednesday, October 10th at 6pm (If you use a "late period", you can turn it in up to Friday, Oct 12th at 6pm). This is an individual work assignment. Sharing of answers or code is strictly prohibited. For the short answer questions, Show your work to document how you came up with your answers. This is one part of a two-part assignment (HW2a and HW2b) due on the same day. Please create a separate PDF file for each part and submit them in electronically via Canvas.

# Part A

Cost and Yield. We talked about cost and yield issues only briefly in class, so this question will introduce you to the cost issues in manufacturing a design.

Your company's fabrication facility manufactures wafers at a cost of \$25,000 per wafer. The wafers are 300mm in diameter (approximately 12 inches). This facility's average defect rate when producing these wafers is 1 defect per 500 mm2 (0.002 defects per mm2).

The first step is to calculate the yield, the percentage of chips manufactured that are free of manufacturing defects using the following yield equation (from the appendix of the Patterson and Hennessy textbook):

Where A is the area of the chip in mm2, D is the defects per mm2, and yield is a number between 0 and 1. Intuitively, this equation shows that if either the area of the chip or the defect rate increases, the yield decreases.

1. Based on this yield equation, what is this facility's yield for chips of 100 mm2, 200 mm2, 400 mm2?

2. Based on the above formula, plot the yield (y-axis) vs the die area of the chip (x-axis). The x-axis should range from zero to 500 mm2; the y-axis should range from 0% to 100%. Plot at least enough plots (say, a few dozen) to generate a smooth curve.

3. Approximately how many good (defect-free) chips can be made from each wafer for chips of 100 mm2, 200 mm2, 400 mm2? (Ignore the "square-peg-in-round-hole" effect.)

4. What is the die manufacturing cost for each of these three chip sizes?

5. Based on the above calculations, on a new graph plot the per-die cost (y-axis) vs the die area of the chip (x-axis). The x-axis should range from zero to 500 mm2; the y-axis should start at zero. Plot at least enough plots (say, a few dozen) to generate a smooth curve.

6. Assuming 5 million transistors per 1 mm2, on a new graph plot the dollars per billion transistors (y-axis) versus the number of transistors per die (in billions) on the x-axis.

7. The above calculation does not include the per-chip cost of packaging. Assuming a \$50 per chip (independent of the size of the chip) additional cost for the package, add another line to the above graph of the cost per billion transistors per die with these costs included.

8. At what transistor count per die is the cost per transistor the lowest? What is the lowest cost (per billion transistors)?

9. To investigate the impact of advancing process generations, now consider a manufacturing process that gives 10 million transistors per 1 mm2, but assume all the other costs and defect rates are the same. Add a third curve to the graph to reflect the new cost-per-transistor of this new generation of manufacturing.

10. With this new data, at what transistor count is the cost per transistor the lowest? What is the lowest cost (per billion transistors)?

11. Although you've calculated the design point with the lowest cost per transistor, why might a company choose to sell a chip with a number of transistors that is smaller or larger than this minimum per-transistor cost point?

What to turn in: Turn the answers to the above questions and three graphs (properly labeled): (1) yield, (2) cost per die, (3) cost-per transistor (with has three curves).