CIS 501 Fall 2005 Class Schedule

This table contains the tentative class schedule. Lecture notes and readings are divided by topic, not by class period.
 
 NOTE: by design, the lecture slides, homeworks, and exams, may not be accessible from outside the .upenn.edu domain.

*** Indicates guest lecturer
 
Class# / Date Topic Readings Assignments
1. 9/8 (R) Introduction
2. 9/13 (T) Technology, Cost, Performance, Power, and Reliability H&P: Chapter 1
Cramming More Components onto Integrated Circuits by Gordon Moore
3. 9/15 (R) Paper Response #1
4. 9/20 (T) Instruction Sets H&P: Chapter 2
The Evolution of RISC Technology at IBM by John Cocke and V. Markstein
5. 9/22 (R) Paper Response #2
6. 9/27 (T)Caches H&P: Chapter 5.1-5.7
Improving Direct-Mapped Cache Performance... by Norm Jouppi
Homework #1
7. 9/29 (R)
8. 10/4 (T) *** Memory H&P: Chapter 5.8-5.18 (skip Intel Pentium example in 5.11 and skim 5.14, 5.15, 5.18)
9. 10/6 (R) Paper Response #3
10. 10/11 (T) Disks and I/O H&P: Chapter 7.1-7.5, 7.7, 7.10, 7.14-16 Homework #2
11. 10/13 (R) Pipelining H&P: Appendix A.1-A.6
Fall Break (T)
12. 10/20 (R)
13. 10/25 (T) Project Description & Review Homework #3
14. 10/27 (R) Midterm Exam - solutions
15. 11/1 (T) Multiple Issue and Static Scheduling H&P: Chapter 4.1, 4.2, 4.3, 4.5 (Conditional or Predicated Instructions), 4.7
Superscalar Instruction Execution in the 21164 Alpha Microprocessor
16. 11/3 (R)
17. 11/8 (T) Out-of-order execution I Paper Response #4
18. 11/10 (R)
19. 11/15 (T) *** Out-of-order execution II H&P: Chapter 3.8-3.9
The Alpha 21264 Processor by R. E. Kessler
20. 11/17 (R) *** Homework #4
Project proposals due Friday, November 18th at 5pm
21. 11/22 (T)Data-Level Parallelism H&P: Appendix G Paper Response #5
Thanksgiving (R)
22. 11/29 (T) Shared-Memory Multiprocessors H&P: Chapter 6.1-6.10
23. 12/1 (R)
24. 12/6 (T)
25. 12/8 (R) Multithreading Project final reports due Friday, December 9th at 5pm
26. 12/16 (F) Final Exam