`timescale 1ns / 1ps module test_full_adder_task_v; // Inputs reg a; reg b; reg cin; // Outputs wire s; wire cout; //Integers (for check tasks) integer errors; // Instantiate the Unit Under Test (UUT) full_adder uut ( .s(s), .cout(cout), .a(a), .b(b), .cin(cin) ); initial begin // Initialize error count errors = 0; // Initialize Inputs a = 0; b = 0; cin = 0; // Wait 100 ns for global reset to finish #100; check_fa(0, 0, 0, 0, 0); check_fa(1, 0, 0, 1, 0); check_fa(0, 1, 0, 1, 0); check_fa(0, 0, 1, 1, 0); check_fa(1, 1, 0, 0, 1); check_fa(1, 0, 1, 0, 1); check_fa(0, 1, 1, 0, 1); check_fa(1, 1, 1, 1, 1); if (errors == 0) begin $display("The simulation completed without errors"); end else begin $display("The simulation failed with %d errors", errors); end end task check_fa; input i_a; input i_b; input i_cin; input exp_s; input exp_cout; begin #25; a = i_a; b = i_b; cin = i_cin; #25; if (s !== exp_s) begin $display("Error at time=%dns s=%b, expected=%b", $time, s, exp_s); errors = errors + 1; end if (cout !== exp_cout) begin $display("Error at time=%dns cout=%b, expected=%b", $time, cout, exp_cout); errors = errors + 1; end end endtask endmodule //test_full_adder_task_v