| Instructor: | Prof. Milo Martin |
|---|---|
| Demo Due: | Thursday, Feb 9th |
| Writeup Due: | Friday, Feb 10th |
| Instructions: | This lab should be done in groups of two or three. |
Before you begin, you'll want to walk through the tutorial.
In this lab, you'll be reverse-engineering a mystery FPGA configuration. The mystery configuration contains a simple combinational logic function of three inputs and two outputs. The three inputs are switches 0, 1 and 2 on component SW7. The outputs are LED 0 and 1 (components D10 and D9).
Your task is to figure out what function this configuration implements (by recording the outputs for all eight possible switch settings) and then write a simple structural Verilog file that implements the exact same function. To load the config file, you'll need to run iMPACT from the Windows Start menu. Once loaded, record the operation of the circuit. Next, follow the Verilog entry instructions from the tutorial, but include in the Verilog file the required logic gates and any need wires. For an example of structural Verilog, see the lectures notes and online resources.
Please write two versions of the module:
The first version of the module, you are restricted to using only strict gate-level structural Verilog using only the simple gates (not, and, or, nand, nor, and xor).
The second version of the module, use assign statements (or initialization of wires) and Verilog operators to simplify your code. Recall the various Verilog operators include:
~, &, |, ^, :?, +, *, etc.
Note
The LED outputs and the switches are both use "active low" signaling. That is, the LED turns on when its signal is a 0 and the LED is off when its signal is a 1. Similarly, The switches return a 1 when off and a 0 when on. You'll need to take this into account when writing your Verilog.
When you've completed and tested your design, demo your design to one of the TAs. They will verify the design works correctly and ask you a few questions about the design. If you pass the demo, they will check you off.
Important
In subsequent labs, all group members must be present at the demo. In this lab, it is okay if not all group members are present.
Turn in the follow items via submitting a single PDF file to blackboard:
A few hints:
In Verilog, various gates (such as and, or, nand, nor) can take multiple inputs. For example, to calculate the "or" of three signals in Verilog:
or (out, in1, in2, in3)
One systematic way to make any combinational logic function is to build a PLA (which were discussed in CIS240). Remember, a PLA has an "and" term for each "one" output in the function. These "and" terms are the "and" of each of the inputs or its inverse. The final answer is the "or " of these "and" terms.