`timescale 1ns / 1ps module test_full_adder_v; // Inputs reg a; reg b; reg cin; // Outputs wire s; wire cout; // Instantiate the Unit Under Test (UUT) full_adder uut ( .s(s), .cout(cout), .a(a), .b(b), .cin(cin) ); initial begin // Initialize Inputs a = 0; b = 0; cin = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here //125 ns #25; a = 1'b1; //150 ns #25; a = 1'b0; b = 1'b1; //175 ns #25; b = 1'b0; cin = 1'b1; //200 ns #25; a = 1'b1; //225 ns #25; a = 1'b0; b = 1'b1; //250 ns #25; a = 1'b1; cin = 1'b0; //275 ns #25; cin = 1'b1; //300 ns #25; a = 1'b0; b = 1'b0; cin = 1'b0; end endmodule // test_full_adder_v