Register File Specification

The register file module will be in the file lc4_regfile.v.:

`timescale 1ns / 1ps

module lc4_regfile(clk, gwe, rst, r1sel, r1data, r2sel, r2data, wsel, wdata, we);
   parameter n = 16;
   
   input clk, gwe, rst;
   input [2:0] r1sel, r2sel, wsel;
   
   input [n-1:0] wdata;
   input we;
   output [n-1:0] r1data, r2data;
   
   wire [n-1:0] r0out, r1out, r2out, r3out, r4out, r5out, r6out, r7out;

   /*** YOUR CODE HERE ***/

endmodule

In a given cycle, any two registers may be read and any register may be written. A register write occurs only when the we signal is high. If the same register is read and written in the same cycle, the old value will be read (not the new value being written).

Register File Schematic

First draw a detailed schematic (by hand or computerized) of the hardware design, including signal names, sub-modules, etc. Only once you have the design on paper in schematic form, then translate it directly to Verilog. That is, your Verilog should correspond to the schematic exactly.

Register File Implementation

You'll build the register file out of a N-bit parametrized register module provided for you, register.v. You may also wish to create your own multiplexor modules based on the lecture notes.

Register File Testing

The testbench for the register file is test_lc4_regfile.tf and the input trace is test_lc4_regfile.input

ALU Specification

The register file module will be in the file lc4_alu.v.

`timescale 1ns / 1ps

module lc4_alu(insn, r1data, r2data, out);
   
   input [15:0] insn, r1data, r2data;
   output [15:0] out;
   
   /*** YOUR CODE HERE ***/

endmodule

The module takes as inputs two 16-bit data values, a 16-bit instruction, and it generates a single 16-bit output. The two data inputs correspond to the two register values coming directly out of the register file. The output will be:

• For basic ALU operations (ADD, MUL, SUB, AND, NOT, OR, XOR, SLL, SRA, SLA, CONST, HICONST, etc.) the output of the ALU is the value the instruction will write back to the register file.
• For memory operations (LDR, STR) the output of the ALU is the generated effective memory address that will be later used as the address input into the data memory.
• For comparison instructions (CMP, CMPU, CMPI, CMPIU), the output will be zero (00000000000000), one (00000000000001), or negative one (1111111111111111), depending on the result of the comparison. This output value will then later be used to set the NZP bits.
• For instructions that use a register value directly (JSRR, JMPR), the first input value should be passed to the output.
• We aren't going to implement DIV and MOD, so those instructions should just return all zeros.
• For all other instructions (NOP, BR, JMP, TRAP, RTI), the output should be all zeros.

If any of the cases are ambiguous, please let us know and we'll clarify.

ALU Schematic

First draw a detailed schematic (by hand or computerized) of the hardware design, including signal names, sub-modules, etc. Only once you have the design on paper in schematic form, then translate it directly to Verilog. That is, your Verilog should correspond to the schematic exactly.

ALU Implementation

To implement the basic operations of the ALU, including + and *, use the built in Verilog operators. To implement the shifter, I suggest implementing a barrel shifter as described in lecture. For signed and unsigned comparisons, consider extending the 16-bit values into 17-bit values (with either zero extend or sign extend, as appropriate), performing the subtraction, and then setting the output accordingly.

ALU Testing

The testbench for the ALU is test_lc4_alu.tf and the input trace is test_lc4_alu.input.