multi-cores c/o Theresa Carle-Sanders

CIS-601-001, Special Topics in Computer Architecture: Security in Multicore Architectures

Spring 2014


Joe Devietti

Office Hours: by appointment in Levine 572

Class discussion and announcements are via Piazza

When & Where

Tuesday/Thursday 10:30-12:00noon, Towne 307

Course Description

The transition to multicore architectures raises new security issues that are not present with uniprocessors. Mutually untrusting workloads running concurrently on distinct cores can interfere with each other via shared structures like caches and memory controllers. This seminar will cover in detail research literature on the sources of interference, the attacks they make possible, and mitigation techniques. Graduate-level coursework in computer architecture (CIS 501) will be very helpful.

Course Materials

No textbooks are required; links to all the papers we read will be provided at this website.


  • Project: 40%
  • Participation: 20%
  • Assignments: 15%
  • Future work write-ups: 15%
  • Reading quizzes: 10%

There will be no exams.

Submit homework, reading quizzes and future-work write-ups via Canvas.

The class project can be done in groups of 2-3. The project is open-ended: it should be something related to information flow or performance isolation in multicores but the specifics are up to you. Choosing a project that incorporates your existing research is a great idea!


This schedule is subject to change

Many of the paper links below are to publisher sites (like the ACM Digital Library). You’ll need to download the papers from an on-campus computer or via the UPenn Library proxy.

Date Topic + Reading Presenter Assignment
Thu 16 Jan Intro Joe
Tue 21 Jan Cache Missing for Fun and Profit Joe
Thu 23 Jan Cache-timing attacks on AES Joe HW1 out
Tue 28 Jan New Branch Prediction Vulnerabilities in OpenSSL and Necessary Software Countermeasures Yuanfeng
Thu 30 Jan Yet Another MicroArchitectural Attack: Exploiting I-cache [CSAW ’07] Akshitha
Tue 4 Feb Introduction to differential power analysis Paul
Thu 6 Feb Performance Isolation Joe HW1 due
Fri 7 Feb Side/covert channels future work write-up due
Tue 11 Feb Addressing Shared Resource Contention in Multicore Processors via Scheduling [ASPLOS ’10] Meng
Thu 13 Feb MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems [HPCA ’13] Laurel
Tue 18 Feb CPI2: CPU performance isolation for shared compute clusters [EuroSys ’13] Liang
Thu 20 Feb Traffic Management: A Holistic Approach to Memory Placement on NUMA Systems [ASPLOS ’13] David
Tue 25 Feb Multicore Resource Management [IEEE Micro ’08] Brooke
Thu 27 Feb A Predictive Model for Cache-Based Side Channels in Multicore and Multithreaded Microprocessors Joe
Fri 28 Feb Performance isolation future work write-up due
Tue 4 Mar no class, ASPLOS
Thu 6 Mar Side-Channel Vulnerability Factor: A Metric for Measuring Information Leakage [ISCA ’12] Kai Project proposals due (project ideas)
Tue 11 Mar no class, spring break
Thu 13 Mar no class, spring break
Tue 18 Mar Countermeasures Joe
Thu 20 Mar New Cache Designs for Thwarting Software Cache-based Side Channel Attacks [ISCA ’07] Brooke & Laurel
Tue 25 Mar Deconstructing New Cache Designs for Thwarting Software Cache-based Side Channel Attacks [CSAW ’08] Yuanfeng & Christian
Thu 27 Mar System-Level Protection Against Cache-based Side Channel Attacks in the Cloud Meng
Fri 28 Mar Secure caches future work write-up due
Tue 1 Apr Complete Information Flow Tracking from the Gates Up [ASPLOS ’09] Paul Project checkpoint due
Thu 3 Apr Execution Leases: A Hardware-Supported Mechanism for Enforcing Strong Non-Interference [MICRO ’09] Akshitha & Liang
Tue 8 Apr Crafting a Usable Microkernel, Processor, and I/O System with Strict and Provable Information Flow Security [ISCA ’11] Sunil
Thu 10 Apr TimeWarp: Rethinking Timekeeping and Performance Monitoring Mechanisms to Mitigate Side-Channel Attacks [ISCA ’12] Christian
Fri 11 Apr Anything goes future work write-up due
Tue 15 Apr Path ORAM: An Extremely Simple Oblivious RAM Protocol [CCS ’13] David & Kai
Thu 17 Apr A Secure Processor Architecture for Encrypted Computation on Untrusted Programs [STC ’12] Sunil
Tue 22 Apr Predictive Black-Box Mitigation of Timing Channels [CCS ’10] Joe
Thu 24 Apr Conclusions Joe
Tue 29 Apr Project presentations
Mon 5 May Project write-ups due