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<h2>CIS 501: Computer Architecture <small>Spring 2019</small></h2>
#### Frequently Asked Questions
This iteration of CIS 501 differs from previous iterations in that we will have the content from [CIS 371: Computer Organization & Design](http://www.cis.upenn.edu/~cis371/18sp/) (most notably the Verilog processor labs). CIS 240 is the pre-requisite, just like for CIS 371.</p>
Here are answers to some common questions about this offering of CIS 501.
+ I'm an undergraduate (in CSCI or CMPE) who needs CIS 371 to graduate. What should I do?
+ You should join [the waitlist](https://forms.cis.upenn.edu/waitlist/index.php). Don't bother with listing CIS 501 for Advance Registration: undergrads cannot register directly for graduate courses (like 501). For undergrads who need CIS 371, the CIS advising staff is working to place them directly into the course. But it's good to join the waitlist just in case.
+ You should also fill out the electronic [CIS Core Requirement Substitution Form](https://forms.cis.upenn.edu/index.php?action=start&form=coresubst01). Note that the *Petition for Action* form is *not* needed.
+ Are other iterations of CIS 501 eligible to stand in for CIS 371 credit?
+ No, only this iteration from Spring 2019.
+ Is the course content the same for graduate and undergraduate students?
+ Yes.
+ I am submatriculating into the CIS MSE. Can I double-count CIS 501 on my undergraduate and graduate degrees?
+ Yes.
+ Why was, in essence, the CIS 371 course number changed this semester?
+ We wanted to offer CIS 501 this academic year. To allow master's and PhD students to take the course, a graduate course number is required.
### Course Information
**instructor**: [Joe Devietti](http://www.cis.upenn.edu/~devietti/)
**when**: Tuesday/Thursday noon-1:30pm
**where**: [Levine Hall](https://www.facilities.upenn.edu/maps/locations/levine-hall-melvin-and-claire-weiss-tech-house) 101 (Wu & Chen Auditorium)
**contact**: [**piazza**](https://piazza.com/class/jp9z30hrmf81u7), [**canvas**](https://canvas.upenn.edu/courses/1435755)
**TAs**:
+ Alexander Do
+ Anastasia Efremkina
+ Grant Moberg
+ Kelly Shiptoski
+ Mara Levy
+ Ming Zhang
+ Stella Ge
+ Steven Bursztyn
**office hours**:
+ Anastasia, Mondays 10:30-12 in K Lab
+ Alex, Anastasia, Grant, Mara, Stella, Steven, Mondays 12:30-4 in [Education Commons](https://commons.library.upenn.edu/node/83) 226
+ Stella & Mara, Tuesdays 1:30-3 in Moore 100A
+ Kelly, Wednesdays 11-12:30 in K Lab
+ Alex, Grant, Ming, Steven, Wednesdays 1-5 in [Education Commons](https://commons.library.upenn.edu/node/83) 226
+ Kelly, Thursdays 10:30-noon in K Lab
+ Joe, Fridays 11:30-1:30pm in K Lab
### Course Description
This is a second computer organization course and focuses on computer hardware
design. In this course you will design and implement a pipelined, superscalar
processor for a simple RISC ISA using Verilog. You will learn the range of
architectural techniques used in modern CPU design including superscalar design,
out-of-order execution, and cache hierarchies.
### Prerequisites
CIS 240 and knowledge of at least one software programming language. We do not
assume you have any prior experience with Verilog.
### Course Materials
The main textbook is *Computer Organization and Design: The Hardware/Software
Interface* by Patterson and Hennessy. The 4th and 5th Editions are both
fine. The 4th Edition is available [for free on-line through the Penn
Library](http://hdl.library.upenn.edu/1017.12/876659).
*Introduction to Logic Synthesis using Verilog HDL* by Reese and Thornton is
also a nice introduction to hardware design and Verilog. It is also available
[as a free PDF via the Penn
Library](http://www.morganclaypool.com/doi/abs/10.2200/S00060ED1V01Y200610DCS006).
[LC4 ISA sheet](lc4.html)
### Course Policies
See details about [course policies on late days, collaboration, etc.](policies.html)
### Lecture slides
Lecture recordings are available via Canvas under **Class Recordings**.
Lecture slides:
+ Introduction ([pptx](slides/01_intro.pptx), [pdf](slides/01_intro.pdf))
+ Hardware ([pptx](slides/02_hardware.pptx), [pdf](slides/02_hardware.pdf))
+ Arithmetic ([pptx](slides/03_arith.pptx), [pdf](slides/03_arith.pdf))
+ Single-Cycle Datapath ([pptx](slides/04_singlecycle.pptx), [pdf](slides/04_singlecycle.pdf))
+ Performance ([pptx](slides/05_performance.pptx), [pdf](slides/05_performance.pdf))
+ Pipelined Datapath ([pptx](slides/06_pipeline.pptx), [pdf](slides/06_pipeline.pdf))
+ Debugging ([pptx](slides/debugging.pptx), [pdf](slides/debugging.pdf))
+ Branch Prediction ([pptx](slides/07_branchprediction.pptx), [pdf](slides/07_branchprediction.pdf))
+ Caches ([pptx](slides/08_caches.pptx), [pdf](slides/08_caches.pdf))
+ Superscalar ([pptx](slides/09_superscalar.pptx), [pdf](slides/09_superscalar.pdf))
+ Out-of-Order ([pptx](slides/10_ooo.pptx), [pdf](slides/10_ooo.pdf))
+ Multicore ([pptx](slides/11_multicore.pptx), [pdf](slides/11_multicore.pdf))
+ Virtual Memory ([pptx](slides/12_virtual_memory.pptx), [pdf](slides/12_virtual_memory.pdf))
+ Meltdown/Spectre ([pptx](slides/meltdown_spectre.pptx), [pdf](slides/meltdown_spectre.pdf))
+ Accelerators ([pptx](slides/13_accelerators.pptx), [pdf](slides/13_accelerators.pdf))
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### Course Schedule
The course schedule is maintained in Canvas. There is [an iCal
feed](https://canvas.upenn.edu/feeds/calendars/user_uIuSzZjAPOAiVyZ4JXqBl4ZNchG6YXL984CY6azF.ics) you can subscribe to with important class events (class meeting times, review sessions, assignment due dates, etc.) Office hours are on [a separate iCal feed](http://www.cis.upenn.edu/~cis501/19sp/cis501oh.ics).
### Previous Editions of CIS 371 and CIS 501
- [CIS 371, Spring 2018](http://www.cis.upenn.edu/~cis371/18sp/)
- [CIS 371, Spring 2017](http://www.cis.upenn.edu/~cis371/17sp/)
- [CIS 371, Spring 2016](http://www.cis.upenn.edu/~cis371/16sp/)
- [CIS 501, Fall 2017](http://cis.upenn.edu/~cis501/previous/fall2017)
- [CIS 501, Fall 2016](http://cis.upenn.edu/~cis501/previous/fall2016)
- [CIS 501, Fall 2015](http://cis.upenn.edu/~cis501/previous/fall2015)
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