[![Haswell die photo, c/o Anandtech](images/HSW_Wafer_03.jpg "Haswell die photo, c/o Anandtech")](http://www.anandtech.com/show/7003/the-haswell-review-intel-core-i74770k-i54560k-tested/5)
CIS 501: Computer Architecture Spring 2015
### Course Information
**instructor**: [Joe Devietti](http://www.cis.upenn.edu/~devietti/)
**when**: Monday/Wednesday 1:30-3:00pm
**where**: Berger Auditorium in the basement of [Skirkanich Hall](http://www.facilities.upenn.edu/maps/locations/skirkanich-hall)
**contact**: [**piazza**](https://piazza.com/class/i4lg7532cd62ex), [**email**](mailto:cis501@cis), [**canvas**](https://canvas.upenn.edu/courses/1270840)
**lecture recordings**: [mediasite](https://ex.cts.isc.upenn.edu/Mediasite/Catalog/Full/1123c78526fe419eaa2f9d14fde06d0821)
**TAs**: Liang Luo and Akshitha Sriraman
**Graders**: Honnesh Ramachandra and Nivedita Velagaleti
+ Liang: Mondays 5-6pm in Levine 5th floor breakout space by elevators
+ Joe: Tuesdays 2-3pm in Levine 572
+ Akshitha: Thursdays 3-4pm in Levine 5th floor breakout space by elevators
### Course Description
This course is a graduate course on computer architecture with an
emphasis on a quantitative approach to cost/performance design
tradeoffs. The course covers the fundamentals of classical and modern
processor design: performance and cost issues, instruction sets,
pipelining, caches, physical memory, virtual memory, I/O superscalar
and out-of-order instruction execution, speculative execution, long
(SIMD) and short (multimedia) vector execution, multithreading, and an
introduction to shared memory multiprocessors.
CIS 501 is a graduate-level course on computer architecture that
assumes significant prior knowledge of computer organization and
architecture. You should already be familiar with hardware caches,
instruction execution pipelines, basic logic design, and some
assembly-level programming. Students are expected to have had a course
that covers the material in a textbook such as Patterson and
Hennessy's "Computer Organization and Design: The Hardware/Software
Interface". Penn's [CIS 371](http://www.cis.upenn.edu/~cis371/) is an
example of such a course.
If you do not have the appropriate background, you should either 1)
not take this class or 2) spend significant time reviewing the
textbook and lecture notes from [CIS 371](http://www.cis.upenn.edu/~cis371/).
### Course Materials
There is *no required textbook* for this course.
For additional review, students may find [Microprocessor Architecture:
From Simple Pipelines to Chip
by Jean-Loup Baer to be helpful. There is an electronic version of
this book at [Cambridge Books
Online](http://dx.doi.org/10.1017/CBO9780511811258) that up to 3
students can view at one time from the Penn network.
If you have no undergraduate coursework in computer architecture you may also want to acquire a copy of Patterson and Hennessy's [Computer Organization and Design: The Hardware/Software Interface](http://textbooks.elsevier.com/web/product_details.aspx?isbn=9780123747501). The Penn Library provides unlimited access to [an online version of this book](http://hdl.library.upenn.edu/1017.12/876659).
Paper Reviews: 5%
Midterm exam: 30%
Final exam: 45%
There will be a **midterm exam** and a **final exam**. The final exam
will be cumulative and will be held during the final time slot for the
course. The final exam will also count as the PhD Architecture WPE I
There will be several **homework assignments**, consisting of problems
to be worked out by hand and/or coding of simulations. You are granted
two 48-hour "grace" periods, and can use at most one per
assignment. If you'd like to use a grace period, just email me and I
will unlock the assignment on Canvas, no questions asked. No
assignment will be accepted after the solutions are posted. Note that
grace periods cannot be used for paper reviews.
There will be several **paper reviews** of academic papers from the
computer architecture research literature. Before we discuss the paper
in class, you will meet in groups to discuss the paper and write a
concise response to a few high-level questions about the paper. To
avoid the same groups for each paper, you may be in a group with a
student at most once.
If you would like a **regrade** of an assignment or exam, you must
email me your request **within 1 week** from the date when grades are
### Academic Misconduct
Academic misconduct such as cheating will not be tolerated. The work
you submit in this class is expected to be entirely your own. If you
submit work that has in part or in whole been copied from some
published or unpublished source (including current or former
students), or that has been prepared by someone other than you, or
that in any way misrepresents somebody else's work as your own, you
will face severe discipline by the university. (Adapted from text
appearing at the Office of Student Conduct page.)
Any detected cases of cheating will be pursued. Penalties can include:
receiving a zero on the assignment (the minimum penalty), failing the
course, having a note placed in your permanent academic record,
suspension, and ultimately expulsion.
See Penn's [Code of Academic
for more information.
### Paper Reviews
1. [Cramming More Components onto Integrated Circuits](papers/mooreslaw-reprint.pdf) by Gordon Moore
2. [Producing Wrong Data Without Doing Anything Obviously Wrong!](papers/producing-wrong-data.pdf) by Todd Mytkowicz, Amer Diwan, Matthias Hauswirth and Peter F. Sweeney
3. [Two-Level Adaptive Training Branch Prediction](papers/two-level-branch-pred.pdf) by Tse-Yu Yeh and Yale Patt.
4. [Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers](papers/jouppi-victim.pdf) by Norm Jouppi
5. [Memory Dependence Prediction using Store Sets](papers/store-sets.pdf) by George Chrysos and Joel Emer
### Important Links
of each lecture are available online.
+ The [trace file format](homework/trace-format.html) used in the homework assignments.
+ [Introduction](slides/01_intro.pptx) [[pdf]](slides/01_intro.pdf)
+ [Trends](slides/02_trends.pptx) [[pdf]](slides/02_trends.pdf)
+ [ISAs](slides/03_isa.pptx) [[pdf]](slides/03_isa.pdf)
+ [Transistors](slides/04_technology.pptx) [[pdf]](slides/04_technology.pdf)
+ [Performance](slides/05_performance.pptx) [[pdf]](slides/05_performance.pdf)
+ [Pipelining](slides/06_pipeline.pptx) [[pdf]](slides/06_pipeline.pdf)
+ [Caches](slides/07_caches.ppt) [[pdf]](slides/07_caches.pdf)
+ [Virtual Memory](slides/08_virtual_memory.pptx) [[pdf]](slides/08_virtual_memory.pdf)
### Course Schedule
*This schedule is subject to change*
### Previous Exams
- [Fall 2013 midterm with solutions](https://www.cis.upenn.edu/~devietti/classes/cis501-fall2013/exams/midterm13-solution.pdf)
- [Fall 2012 midterm](https://www.cis.upenn.edu/~devietti/classes/cis501-fall2013/exams/midterm12.pdf), [solutions](https://www.cis.upenn.edu/~devietti/classes/cis501-fall2013/exams/midterm12-solution.pdf)
+ [Fall 2013 final with solutions](https://www.cis.upenn.edu/~devietti/classes/cis501-fall2013/exams/final13-rubric.pdf)
+ [Fall 2012 final](https://www.cis.upenn.edu/~devietti/classes/cis501-fall2013/exams/final12.pdf), [solutions](https://www.cis.upenn.edu/~devietti/classes/cis501-fall2013/exams/final12-solution.pdf)
### Previous Editions of CIS 501
- [Fall 2013](http://cis.upenn.edu/~devietti/classes/cis501-fall2013/)
- [Fall 2012](http://www.cis.upenn.edu/~milom/cis501-Fall12/)
- [Fall 2011](http://www.cis.upenn.edu/~milom/cis501-Fall11/)