<div class="alert alert-danger" role="alert"> <strong>CIS 371 has been renumbered to CIS 471/571. Read more at the <a href="https://www.cis.upenn.edu/~cis471/">CIS 471 homepage</a>.</strong> </div> <!-- <div class="alert alert-danger" role="alert"> <strong>If you are not registered for CIS 501 but would like to please join <a href="https://forms.cis.upenn.edu/waitlist/index.php">the waitlist</a>.</strong> </div> <div class="alert alert-danger" role="alert"> <strong>Be sure to <a href="https://piazza.com/upenn/spring2020/srs_cis3710012020a">join the CIS 371 Piazza forum</a></strong> so you don't miss important announcements! </div> --> ![Intel Ice Lake die photo, c/o WikiChip](images/ice_lake_die.png "Intel Ice Lake die photo, c/o WikiChip") <h2>CIS 371: Computer Organization and Design <small>Spring 2020</small></h2> ### Course Information **instructor**: [Joe Devietti](http://www.cis.upenn.edu/~devietti/) **when**: Tuesday/Thursday 1:30-3pm **where**: [Towne Building](https://www.facilities.upenn.edu/maps/locations/towne-building), Room 100 (aka Heilmeier Hall) **contact**: [piazza](piazza.com/upenn/spring2020/srs_cis3710012020a/home), [canvas](https://canvas.upenn.edu/courses/1493255) **TAs**: + Alexander Do + Aliza Gindi + Eric Giovannini + Brandon Gonzalez + Grant Moberg + Sehyeok Park + Shreyas Shivakumar **office hours** (all times US Eastern, see Piazza for Zoom meeting details): + Monday, 3-4:30pm - Shreyas + Monday, 4-5:30pm - Eric + Tuesday, noon-1:30pm - Alex + Tuesday, 1:30-3pm - Joe + Tuesday, 3-4:30pm - Grant + Wednesday, 9:30-11:30am - Aliza, Shreyas + Wednesday, 4-5:30pm - Eric + Wednesday, 8-9:30pm - Sehyeok + Thursday, 10am-noon - Aliza + Thursday, noon-1:30pm - Alex + Thursday, 1:30-3pm - Joe + Thursday, 3-4:30pm - Grant + Friday, 3-4:30pm - Sehyeok + Saturday, 12-2PM and 3-5PM - Brandon See also [the CIS 371 office hours calendar feed](http://www.cis.upenn.edu/~cis371/spring2020/cis371oh.ics). ### Course Description This is a second computer organization course and focuses on computer hardware design. In this course you will design and implement a pipelined, superscalar processor for a simple RISC ISA using Verilog. You will learn the range of architectural techniques used in modern CPU design including superscalar design, out-of-order execution, and cache hierarchies. ### Prerequisites CIS 240 and knowledge of at least one software programming language. We do not assume you have any prior experience with Verilog. ### Course Materials The main textbook is *Computer Organization and Design: The Hardware/Software Interface* by Patterson and Hennessy. The 4th and 5th Editions are both fine. The 4th Edition is available [for free on-line through the Penn Library](http://hdl.library.upenn.edu/1017.12/876659). *Introduction to Logic Synthesis using Verilog HDL* by Reese and Thornton is also a nice introduction to hardware design and Verilog. It is also available [as a free PDF via the Penn Library](http://www.morganclaypool.com/doi/abs/10.2200/S00060ED1V01Y200610DCS006). [LC4 ISA sheet](lc4.html) ### Course Policies See details about [course policies on late days, collaboration, etc.](policies.html) ### Lecture slides Lecture recordings are available via Canvas under **Class Recordings**. Lecture slides: + Introduction ([pptx](slides/01_intro.pptx), [pdf](slides/01_intro.pdf)) + Hardware ([pptx](slides/02_hardware.pptx), [pdf](slides/02_hardware.pdf)) + Arithmetic ([pptx](slides/03_arith.pptx), [pdf](slides/03_arith.pdf)) + Single-Cycle Datapath ([pptx](slides/04_singlecycle.pptx), [pdf](slides/04_singlecycle.pdf)) + Performance ([pptx](slides/05_performance.pptx), [pdf](slides/05_performance.pdf)) + Pipelined Datapath ([pptx](slides/06_pipeline.pptx), [pdf](slides/06_pipeline.pdf)) + Branch Prediction ([pptx](slides/07_branchprediction.pptx), [pdf](slides/07_branchprediction.pdf)) + Debugging ([pptx](slides/debugging.pptx), [pdf](slides/debugging.pdf)) + Caches ([pptx](slides/08_caches.pptx), [pdf](slides/08_caches.pdf)) + Superscalar ([pptx](slides/09_superscalar.pptx), [pdf](slides/09_superscalar.pdf)) + Out-of-Order ([pptx](slides/10_ooo.pptx), [pdf](slides/10_ooo.pdf)) + Multicore ([pptx](slides/11_multicore.pptx), [pdf](slides/11_multicore.pdf)) + Virtual Memory ([pptx](slides/12_virtual_memory.pptx), [pdf](slides/12_virtual_memory.pdf)) + Accelerators ([pptx](slides/13_accelerators.pptx), [pdf](slides/13_accelerators.pdf)) <!-- + Meltdown/Spectre ([pptx](slides/meltdown_spectre.pptx), [pdf](slides/meltdown_spectre.pdf)) --> ### Course Schedule The course schedule is maintained in Canvas. There is [an iCal feed](https://canvas.upenn.edu/feeds/calendars/user_uIuSzZjAPOAiVyZ4JXqBl4ZNchG6YXL984CY6azF.ics) you can subscribe to with important class events (class meeting times, review sessions, assignment due dates, etc.) ### Previous Editions of CIS 501 and CIS 371 - [CIS 501, Fall 2019](http://cis.upenn.edu/~cis501/previous/fall2019) - [CIS 501, Spring 2019](http://cis.upenn.edu/~cis501/previous/spring2019) - [CIS 371, Spring 2018](http://www.cis.upenn.edu/~cis371/18sp/) - [CIS 371, Spring 2017](http://www.cis.upenn.edu/~cis371/17sp/) - [CIS 371, Spring 2016](http://www.cis.upenn.edu/~cis371/16sp/)