| email |
santoshn at figure out the domain name |
| office |
| address |
614, Levine Hall, 3330 Walnut Street, |
| |
Philadelphia, PA 19104 |
About me
I
am a fifth year PhD student in the Computer and Information
Sciences department at the University of Pennsylvania.
I am advised by Milo Martin.
I interned at Microsoft Research with Madan Musuvathi and Sebastian Burckhardt from June-September 2009.
Research Interests
I am interested in building
efficient, robust and secure software systems. Primary research
interests are in hardware-software interfaces spanning programming
languages, compilers, runtimes and computer architecture. I love
working on the entire computing stack ranging from hardware modifications,
operating system enhancements, compiler optimizations and programming
language design to build robust systems.
Job Application Materials
I plan to graduate in Summer 2012. I am actively looking for tenure
track assistant professor positions in research oriented universities.
CV (last updated: February 2012)
Research statement
Teaching statement
Collaborators
Sebastian Burckhardt,
R Govindarajan,
Andrew Hilton,
Pravesh Kothari,
Milo Martin,
Madanlal Musuvathi,
Amir Roth ,
Steve Zdancewic ,
Jianzhou Zhao.
Current Projects
- Memory safety for C and
C++: SoftBound/CETS
Proposed compiler and hardware instrumentation to provide
complete spatial and temporal memory safety for C/C++ programs
with a low overhead. A prototype is available for
download.
Download
here
- Concurrency Bug Detection with Guarantees:
NeedlePoint/PCT/PPCT
We have proposed concurrency bug
techniques that provide mathematical guarantees of triggering
the bug. We have built a framework called NeedlePoint that
provides basic mechanisms to implement a wide variety of bug
detection and experimentally evaluate them.
- Vellvm:
Verified LLVM:
Verifying LLVM, an industrial
strength compiler. We have formalized the semantics of the LLVM IR
and are working on verifying optimizations in the LLVM suite.
- iCFP: Inorder Continual Flow Pipeline
iCFP
is a micro-architecture technique to make in-order processors,
cache miss tolerant at all levels
- Finding bugs in Distributed Systems
Publications
Peer Reviewed
-
Multicore Acceleration for Priority Based Schedulers for Concurrency Bug Detection[pdf]
Santosh Nagarakatte, Sebastian Burckhardt, Milo M K Martin, Madan Musuvathi
To Appear in the Proceedings of the 2012 ACM SIGPLAN Conference on Programming Language Design and Implementation( PLDI 2012), June 2012
Acceptance Rate: 19% (48 out of 255 submissions)
- Formalizing the LLVM Intermediate Representation for
Verified Program Transformations
[pdf]
Jianzhou Zhao, Santosh Nagarakatte,
Milo M K Martin and Steve Zdancewic
Proceedings of the 39th ACM SIGPLAN-SIGACT Symposium on
Principles of Programming
Languages( POPL
2012), January, 2012
Acceptance Rate: 21% (44 out of 205 submissions)
- CETS: Compiler Enforced Temporal Safety for
C [pdf]
Santosh
Nagarakatte, Jianzhou Zhao, Milo M K Martin and Steve
Zdancewic
Proceedings of International Conference on Memory
Management (ISMM
2010), June, 2010
Acceptance Rate: 43% (13 out of 30 submissions)
- A Randomized Scheduler with Probabilistic Guarantees
of Finding Concurrency Bugs
[pdf]
Sebastian Burckhardt, Pravesh
Kothari, Madanlal Musuvathi, and Santosh Nagarakatte
Proceedings of International Conference on Architectural
Support for Programming Languages & Operating Systems
(ASPLOS
2010), March, 2010
Acceptance Rate: 17% (32 out
of 181 submissions)
- iCFP: Tolerating All-Level Cache Misses in In-Order
Processors [pdf]
Andrew Hilton, Santosh Nagarakatte, and Amir Roth
IEEE MICRO's "Top Picks of Architecture Conferences of 2009" Issue(Micro Top Picks'10)
January-February 2010
- SoftBound: Highly Compatible and Complete Spatial
Memory Safety for
C [pdf]
Santosh Nagarakatte, Jianzhou Zhao, Milo M K Martin, Steve
Zdancewic
In the Proceedings of ACM SIGPLAN
Conference on Programming Language Design and Implementation
(PLDI), June
2009
Acceptance Rate: 21% (41 out of 196 submissions)
- iCFP: Tolerating All-Level Cache Misses in
In-Order Processors [pdf]
Andrew Hilton, Santosh Nagarakatte, Amir Roth
Proceedings of the 15th International
Symposium on High Performance Computer Architecture (HPCA), Feb
2009
Acceptance Rate: 19% (35 out of 184 submissions)
- Register Allocation and Optimal Spill Code
Scheduling in SWP loops
Santosh Nagarakatte, R. Govindarajan
Proceedings of the 16th International Conference on Compiler
Construction (CC),
March 2007
Acceptance Rate: 23% (14 out of 60 submissions)
In Submission
- Watchdog: Hardware for Safe and Secure Manual Memory Management and Full Memory Safety[pdf]
Santosh Nagarakatte, Milo M K Martin, Steve Zdancewic
In Submission, November 2011
In Preparation
- Mechanized Verification of SSA Optimizations[pdf]
Jianzhou Zhao, Santosh Nagarakatte, Milo M K Martin, Steve Zdancewic
Reports
- SoftBound: Highly Compatible and Complete
Spatial Memory Safety for C [pdf]
Santosh Nagarakatte, Jianzhou Zhao, Milo M K Martin, Steve
Zdancewic
University of Pennsylvania Technical Report MS-CIS-09-01, January 2009
- A Randomized Scheduler with Probabilistic Guarantees of Finding Bugs [pdf]
Sebastian Burckhardt, Pravesh Kothari, Madanlal Musuvathi, Santosh Nagarakatte
Microsoft Research Technical Report MSR-TR-2010-3, January 2010
Teaching
I was the TA for CIS
371 in Spring 2009
and CIS 501 in Fall
2008.
I gave a guest lecture on Virtual Memory and Superscalar
processors for CIS 501 in Fall 2010.
I gave a guest lecture on Mace and MaceMC for CIS 800 in Fall 2011.
Biography
I obtained my B.E in Computer Engg. and M.S(Engg) from the
National
Institute of Technology, Karnataka, Surathkal (NITK/KREC) and the Indian Institute of
Science, Bangalore respectively.
Awards and Honors
- Paper in IEEE Micro's Top Picks Issue 2010
- University Gold Medal by NITK Surathkal for the excellent
academic performance in Computer Engineering for the period 2001-2005
- Philips Research Fellowship by Philips and IISc for
the period 2005-2007
- University of Pennsylvania Graduate Fellowship
Conference/Invited Talks
- NeedlePoint: A Framework to Expose Concurrency Bugs by Controlling Thread Interleavings at the Indian Institute of Science (IISc), Bangalore, India, April 2011
- NeedlePoint: A Framework to Expose Concurrency Bugs by Controlling Thread Interleavings at Systems Lunch, Penn, Philadelphia, March 2011
- CETS: Compiler Enforced Temporal Safety for C at ISMM 2010, Toronto, June 2010
- SoftBound: Highly Compatible and Complete Spatial Memory Safety for C at Microsoft Research India, Bengaluru, December 2009
- SoftBound: Highly Compatible and Complete Spatial Memory Safety for C at LLVM Developer's Meeting, Cupertino, CA, October 2009 [video]
- A Randomized Scheduler for Finding Concurrency Bugs at Microsoft Research, Redmond, September 2009
- SoftBound: Highly Compatible and Complete Spatial Memory Safety for C at PLDI, Dublin, Ireland, June 2009
- Register Allocation and Optimal Spill Code Scheduling at CC 2007, Braga, Portugal, March 2007
Conferences Attended
- POPL 2012, Philadelphia, USA
- PLDI 2011, San Jose, USA
- ISMM/PLDI 2010, Toronto, Canada
- ASPLOS 2010, Pittsburgh, USA
- HPCA/PPOPP 2010, Bangalore, India
- PLDI 2009, Dublin, Ireland
- HPCA 2009, Raleigh, USA
- CC/ETAPS 2007, Braga, Portugal
Course work & WPE
- CIS 500, Software Foundations (Fall 2007)
- CIS 501, Computer Architecture (Fall 2007)
- CIS 670, Program Analysis (Fall 2007)
- CIS 502, Analysis of Algorithms (Spring 2008)
- CIS 505, Software Systems (Spring 2008)
- CIS 640, Introduction to Multiprocessor Programming (Spring 2009)
- CIS 700, Distributed Systems meet Social Networks (Spring 2010)
- My WPE-II exam was on Deterministic Multithreading in Spring 2010
Activities
I love racquet sports. I play
squash three or four times a week. I also read a lot of
non-technical books. Inspired by Adam
Chilpala's book log, a log of the books I have recently read is
available here.
Charity
I generally support one or two charity
organizations every year that are currently performing amazing work
that ameliorates the condition of the human race. Kindly consider
supporting
Doctors Without
Borders and Association for
India's Development's Eureka Project.
