Lab 0 - Getting Started

CSE 372 (Spring 2007): Digital Systems Organization and Design Lab

Due Friday, Feburary 2nd (write up is due in class, you must demo it in the KLab by 7pm)

This lab should be done in groups of two or three.

This lab is worth 10 points.


Before you begin, you'll want to walk through the tutorial.

In this lab, you'll be reverse-engineering a mystery FPGA configuration. The mystery configuration contains a simple combinational logic function of three inputs and two outputs. The three inputs are switches 0, 1 and 2 on component SW7. The outputs are LED 0 and 1 (components D10 and D9).

Your task is to figure out what function this configuration implements (by recording the outputs for all eight possible switch settings) and then write a simple structural Verilog file that implements the exact same function. To load the config file, you'll need to run iMPACT from the Windows Start menu. Once loaded, record the operation of the circuit. Next, follow the Verilog entry instructions from the tutorial, but include in the Verilog file the required logic gates and any need wires. For an example of structural Verilog, see the two "HDL" slides from lectures notes from the first day of class. The simple gates available are: not, and, or, nand, nor, and xor.


In this lab you can only use structural Verilog and only these six gate types: not, and, or, nand, nor, and xor


The LED outputs and the switches are both use "active low" signaling. That is, the LED turns on when its signal is a 0 and the LED is off when its signal is a 1. Similarly, The switches return a 1 when off and a 0 when on. You'll need to take this into account when writing your Verilog.


When you've completed and tested your design, demo your design to one of the TAs. They will verify the design works correctly and ask you a few questions about the design. If you pass the demo, they will check you off.


If you do this as a group, all group members must be present at the demo.

What to Turn In

Turn in the follow items in class:


A few hints: