Testing Verilog Designs for Fun and Profit


Testing, you may have noticed, is painful. In an effort to make the process slightly less so, your friendly CSE 372 TA's have put together a testbench framework using behavioral Verilog. The testbench is available here: lab1_testbench.v.

The code is very straightforward: the Unit Under Test (UUT) is instantiated at the top. The testbench code basically just reads a series of values from a file (named, by default, lab1.input.test) to send as input to the UUT. Expected output values are also read from this file, and compared with the UUT's actual output.

To make the testbench work, make sure you have both the testbench verilog module and the test input file. Both can reside in the main directory of your Xilinx project, and they should work fine for both Xilinx and ModelSim.

Currently, the file lab1.input.test is pretty skimpy - feel free to flesh it out with your own test cases.


  1. Lines in the test input file that begin with a "#" (sh) character are ignored as comments (but see "Caveats" below)
  2. Currently, values read from the test input file (other than the control signal for the ALU) must be in decimal.


When a comment is read from the test input file, it causes the ALU control signal to dip to 0x0000 temporarily. This is usually not an issue, as 0x0000 is an invalid control signal, but if you write many lines of comments in succession, this can cause some bizarre timing issues.