Lab 2 - Register File

CSE 372 (Spring 2006): Digital Systems Organization and Design Lab

Demo by 7pm Friday, February 17th.

Writeup due before class on Monday, February 20th.

This lab is to be done individually.

This lab is worth 10 points.


In this lab, you will construct the register file for a P37X ISA processor.


This lab is significantly less work than lab 1, so it is worth fewer points.

Register Building Block

As discussed in class, all of the state elements in your eventual P37X processor will use the same low-level flip-flop primitive. This flip-flop has a clock input signal, a synchronous reset signal, and an explicit write-enable signal. The module is also parameterized to easily allow you to make n-bit registers. The Verilog code:

module register (out, in, wen, rst, clk);
  parameter n = 1;

  output [n-1:0] out;
  input [n-1:0] in;
  input wen;
  input rst;
  input clk;

  reg [n-1:0] out;

  always @(posedge clk) 
      if (rst) 
        out = 0; 
      else if (wen) 
        out = in; 

Register File Interface

The P37X ISA uses eight registers and follows a two-input, one-output operation format. As such, the register file should have eight registers accessed via two read ports and one write port. Your register file module regfile8_16_2r1w should have the following interface:

In a given cycle, any two registers may be read and any register may be written. A register write occurs only when the wen signal is high. If the same register is read and written in the same cycle, the old value will be read (not the new value being written).

Register File Implementation

Implement the register file as described in the CSE371 lecture notes on datapath design. Each read port uses a 16-bit 8-to-1 multiplexor to select the outputs of one of the eight 16-bit registers. The write port uses the output of a 3-to-8 decoder combined with the write enable input to drive the write enable on the individual register's write enable signals. You need not use tri-state devices, because Xilinx should detect the multiplexors and generate its own fast multiplexors (assuming your Verilog code is clean enough).

As before, we'll use a multi-level modular design:

1. 16-bit 8-to-1 Multiplexor

As we'll need two multiplexors in our register file, make a separate multiplexor structural module. You're allowed (and encouraged) to use the nested conditional operator to create the multiplexor. As such a multiplexor will be a useful primitive for later, I suggest you make the width of the multiplexor parameterizable.

2. 3-to-8 Decoder

The decoder has a single 3-bit input and a single 8-bit output. Recall that exactly one of outputs of a decoder is one; the rest will be zero. If the 3-bit input value is n, then the nth is the bit set to one. As with the multiplexor, the use of the nested conditional operator should make this structure relatively easy to specify in Verilog.

3. Register File

Create a register file module with the interface specified above. Before you write the Verilog code for the register file, first draw a diagram of the circuit with all wires and input/outputs labeled. Include this hand-drawn schematic with your lab writeup.

Now that you've built the multiplexor and decoder, this module should be also be straightforward. You'll instantiate eight registers, one decoder, and two multiplexors and then connect them as needed. You'll also need to use the global write enable signal along with the output of the decoder to the write enable of each of the register's write enable input.


Test your register file using ModelSim using your own test signals and/or your own behavioral testbench. Later this week we'll give you a more elaborate and extensive testbench environment (as we did with lab 1) for further testing your design.

Note: A "Beta" version of the testbench and input file are now available: lab2_testbench.v and lab2.input.test

You should verify that your design fully synthesizes without error, but you do not need to explicitly test the register file using the board.


Similar to the demo for lab 1, the TAs will run an additional test input file to test additional cases. No demonstration directly involving the board will be required.

What to Turn In

Turn in:

  1. Verilog code. As before, your Verilog code should be well-formatted, easy to understand, and include comments where appropriate (for example, use comments to describe all the inputs and outputs to your Verilog modules). Some part of the project grade will be dependent on the style and readability of your Verilog, including formatting, comments, good signal names, and proper use of hierarchy.
  2. Hand-drawn schematic. Turn in a schematic for the register file. You need not turn in schematics for the multiplexor or decoder.

In addition, answer the following questions. When reporting timing results, use the information from the "Post Place and Route Timing" report.

  1. What is the delay (in nanoseconds) and resource usage for your register file. How do these compare to the delay and resource usage of your ALU?
  2. What problems, if any, did you encounter while doing this lab?
  3. How many hours did it take you to complete this assignment? On a scale of 1 (least) to 5 (most), how difficult was this assignment?

Honor Points

I can't think of any interesting extentions to this lab, so unless someone in the class has any suggestions, there will be no honors points for this assignment.