`timescale 1ns / 1ps `define EOF 32'hFFFF_FFFF `define NEWLINE 10 `define NULL 0 `ifndef INPUT `define INPUT "test_lc4_branch_unit.input" `endif `define OUTPUT "test_lc4_branch_unit.output" module testbench_v; integer input_file, output_file, errors, linenum; // Inputs reg [15:0] insn; reg [15:0] pc; reg [2:0] nzp; reg [15:0] rs_data; // Outputs wire [15:0] next_pc; // Instantiate the Unit Under Test (UUT) lc4_branch_unit branch_unit (.insn(insn), .pc(pc), .nzp(nzp), .rs_data(rs_data), .next_pc(next_pc)); reg [15:0] expected_out; initial begin // Initialize Inputs insn = 0; pc = 0; nzp = 0; rs_data = 0; errors = 0; linenum = 0; output_file = 0; // open the test inputs input_file = $fopen(`INPUT, "r"); if (input_file == `NULL) begin $display("Error opening file: ", `INPUT); $finish; end // open the output file `ifdef OUTPUT output_file = $fopen(`OUTPUT, "w"); if (output_file == `NULL) begin $display("Error opening file: ", `OUTPUT); $finish; end `endif // Wait for global reset to finish #100; #2; while (5 == $fscanf(input_file, "%h %h %d %h %h", pc, insn, nzp, rs_data, expected_out)) begin #8; linenum = linenum + 1; if (output_file) begin $fdisplay(output_file, "%h %h %d %h %h", pc, insn, nzp, rs_data, next_pc); end if (expected_out !== next_pc) begin $display("Error at line %d: insn = %h, pc = %h, nzp = %b, rs_data = %h, output value should have been %h, but was %h instead", linenum, insn, pc, nzp, rs_data, expected_out, next_pc); errors = errors + 1; end #2; end // end while if (input_file) $fclose(input_file); if (output_file) $fclose(output_file); $display("Simulation finished: %d test cases %d errors [%s]", linenum, errors, `INPUT); $finish; end endmodule