Instructor: | Prof. Milo Martin |
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Demo Due: | Thursday, March 3rd (you must demo it in the KLab by 7pm) |
Writeup Due: | Friday, March 4th (turn in PDF via Blackboard) |
Instructions: | This lab should be done in groups of two or three. |
This lab is worth 7% of your course grade.
In this lab, you'll create two key components of the processor: the register file and the ALU for the LC4. We're providing the Verilog module definitions and testing harness to help you test your designs in ModelSim. The testbench code uses Verilog file I/O and other advanced features of Verilog, which is why we've provided it to you.
ModelSim is the software we'll use for simulating and debugging Verilog. You'll want to work through the ModelSim tutorial and look at the ModelSim tips document.
The LC4 ISA uses eight registers and follows a two-input, one-output operation format. As such, the register file should have eight registers accessed via two read ports and one write port. The lecture notes contain a four-element register file, so this design is just a small variant on that, so this part hopefully shouldn't take you long.
The register file module will be in the file lc4_regfile.v.:
`timescale 1ns / 1ps module lc4_regfile(clk, gwe, rst, r1sel, r1data, r2sel, r2data, wsel, wdata, we); parameter n = 16; input clk, gwe, rst; input [2:0] r1sel, r2sel, wsel; input [n-1:0] wdata; input we; output [n-1:0] r1data, r2data; wire [n-1:0] r0out, r1out, r2out, r3out, r4out, r5out, r6out, r7out; /*** YOUR CODE HERE ***/ endmodule
In a given cycle, any two registers may be read and any register may be written. A register write occurs only when the we signal is high. If the same register is read and written in the same cycle, the old value will be read (not the new value being written).
Note
The "GWE" signal is a global write-enable (one write enable signal that controls every state variable in the design). For now, just pass this along into the N-bit register. In the next lab, you'll use this to single-step your design when debugging it on the FPGA boards.
First draw a detailed schematic (by hand or computerized) of the hardware design, including signal names, sub-modules, etc. Only once you have the design on paper in schematic form, then translate it directly to Verilog. That is, your Verilog should correspond to the schematic exactly.
You'll build the register file out of a N-bit parametrized register module provided for you, register.v. You may also wish to create your own multiplexor modules based on the lecture notes.
The testbench for the register file is test_lc4_regfile.tf and the input trace is test_lc4_regfile.input
The LC4 ALU module performs all of the arithmetic and logical operations for the various instructions. In this lab you'll build a self-contained ALU datapath with the corresponding control signals.
The register file module will be in the file lc4_alu.v.
`timescale 1ns / 1ps module lc4_alu(insn, r1data, r2data, out); input [15:0] insn, r1data, r2data; output [15:0] out; /*** YOUR CODE HERE ***/ endmodule
The module takes as inputs two 16-bit data values, a 16-bit instruction, and it generates a single 16-bit output. The two data inputs correspond to the two register values coming directly out of the register file. The output will be:
If any of the cases are ambiguous, please let us know and we'll clarify.
First draw a detailed schematic (by hand or computerized) of the hardware design, including signal names, sub-modules, etc. Only once you have the design on paper in schematic form, then translate it directly to Verilog. That is, your Verilog should correspond to the schematic exactly.
To implement the basic operations of the ALU, including + and *, use the built in Verilog operators. To implement the shifter, I suggest implementing a barrel shifter as described in lecture. For signed and unsigned comparisons, consider extending the 16-bit values into 17-bit values (with either zero extend or sign extend, as appropriate), performing the subtraction, and then setting the output accordingly.
Important
Let me repeat, you do not need to write your own adder or multiplier. Just use the builtin + and * operators.
The testbench for the ALU is test_lc4_alu.tf and the input trace is test_lc4_alu.input.
This synthesizable part of this lab should be implemented using the structural and behavioral Verilog subset as in presented in the class notes. The only state element you are allowed to use for synthesis is Nbit_reg. If you're not sure if you're allowed to use a certain Verilog construct, just ask (post a message on the newsgroup, send an e-mail, etc.).
You'll show the TAs your schematics, your code, and demonstrate that your design works using the simulation testbenches.
Important
All group members should be present at the demo.
Turn in a single PDF to BlackBoard that contains all of the following: