Advanced Computer Architecture Discussion Group
Spring 2006
In the Spring of 2006, a group met weekly (Thursays at 2pm in Levine 512) to
discuss advanced topics in computer architecture such as cache coherence,
memory consistency models, multi-core processors, and models for expressing
parallelism.
- Thursday, Feb 9th:
- Thursday, Feb 16th:
- Thursday, Feb 23rd:
- Thursday, Mar 2nd:
- Thursday, Mar 9th: spring break
- Thursday, Mar 16th:
- Thursday, Mar 23rd:
- Overview of Memory Consistency Models
- Thursday, Mar 30th:
- Thursday, Apr 6th:
- Thursday, Apr 13th:
One possible source for specific papers is the seminar course from a couple of
years ago: CIS 700 Special Topic: Multiprocessor Computer Architecture &
Server Workloads.
- Lock-based synchronization
- Speculative synchronization (SLE/TLR)
- Transactional memory
- Power 4/Power 5
- Hydra
- Piranha
- Heterogeneous multi-cores (ISCA 2005 papers, especially)
- Niagara: A 32-Way Multithreaded SPARC Processor, Poonacha Kongetira,
Kathirgamar Aingaran, and Kunle Olukotun, IEEE Micro, pp. 21-29, March/April
2005. http://ogun.stanford.edu/~kunle/publications/niagra_micro.pdf
- J. D. Davis, et al., Maximizing CMT Throughput with Mediocre Cores, 14th
Int. Conf. Parallel Architectures and Compilation Techniques (PACT), Sep.
2005, pages 51-62.
- IBM's Cell architecture (used in the PlayStation 3)
- The Xbox 360 processor (which is much more conventional than the Cell).
- SafetyNet
- Flight Data Recorder (FDR)
- BugNet
- Various papers from YYZ's group at UIUC
- Graphics processors (GPUs)
- Google's Map/Reduce model
- Stream-based models of Parallelism
- Desktop parallelism (ASPLOS paper from Michigan)
- Video encoding
- Speech recognition
- Games
- 3D graphics (physical-based modeling)
- Crypto and security
- CAD and software verification