GUEST EDITORIAL
Special Issue of IEEE Journal of Selected Areas in Communications on 
            High Speed Computer/Network Interfaces


	The last decade has seen an enormous increase in the
performance of processors and the communications networks with which
they are connected. To deliver high performance to applications,
careful design of the computer/network interface is needed to ensure
that a system performance bottleneck is not created. This issue of the
IEEE Journal on Selected Areas in Communications is focused on
High Speed Computer/Network Interconnection. The developments of
very high-speed networks and high-performance computers have forced
engineering research into the design, implementation, performance
analysis and experimental evaluation of these interconnects, as they
would otherwise pose a fundamental bottleneck to applications. Our
belief that this topic was of great interest to the scientific
community was confirmed by the number of high-quality papers
submitted to the special issue.  Thirty papers were submitted for
consideration by the Guest Editors, and ten papers were selected
for the issue. More high-quality papers were received than could
be published.
	Design of such interfaces has been a hard problem faced by
researchers in the past, in particular in the case of Local-Area
Networks, where the introductions of Ethernet and FDDI placed
significant strains on architects of computers and high-performance
communications subsystems. The first paper, by Robert Metcalfe, offers
a number of key observations and lessons learned in the design and
implementation of many generations of computer/network
interconnects. Of particular interest to other researchers will be the
discussion of mistakes, to prevent traveling these paths again; Metcalfe's
remarks are clearly relevant to host interfacing in general as well
as the specifics of ARPAnet and Ethernet interfaces.
	The second paper, by Floyd Ross, discusses the computer
communications issues which drove many design considerations in the
FDDI standardization process, including host/computer interconnection.
Two other papers in this issue discuss FDDI implementations and
performance analyses, putting the FDDI design through exploratory
hurdles.
	The paper by David Banks and Michael Prudence describes an
implementation of an FDDI interface for workstations and the software
architecture used to offer high performance to applications. They
present performance data for the implementation ; the data suggests
that a protocol hierarchy which reduces data copying will provide
higher performance when network speeds are in the range of workstation
memory bandwidths.
	``Performance Considerations in Designing Network
Interfaces'', by K.  K. Ramakrishnan presents an interesting study of
a computer/network interface design and its performance using the FDDI
token-ring as a case study.
	``Consideration of a Multiprocessor Approach for Meeting the
Processing Requirements for OSI'' by M. Ito, L. Takeuchi and G.
Neufeld studies a parallel processing approach for processing OSI
layers 2 through 6 using the packet as the unit of parallelism.  The
work offers insight into the feasibility and complexity of this
problem.
	Many future broadband communications networks are expected to
employ Asynchronous Transfer Mode (ATM) technology, which is based on
the transmission of data as small, fixed-size ``cells''. While the
cell parameters are attractive for priorities, multiplexing and
robustness in traffic mixes, the size presents a problem for
computer/host interconnects. Small sizes force large overheads for
interrupt service and bus transactions on the host processor, thus ATM
interface solutions must address this problem to achieve high
performance.  The ATM interfaces face another change of environment in
contrast to traditional network architectures composed of LANs
interconnected by WANs. In particular, traffic characteristics
expected cannot be easily used to optimize designs for specific LAN or
WAN parameters such as burstiness. This will be true because ATM is
essentially LAN/WAN transparent, and as of yet, most applications are
proposed and thus have not had an opportunity to become
well-understood by designers.
	Davie's paper describes an ATM host interface for the
DEC TURBOchannel, designed to support 622 Mbit/sec SONET links.  To
the editor's knowledge, this is the highest-performance workstation
ATM interface built to date.
	The paper by Traw and Smith presents the
hardware architecture of an ATM interface for IBM's Micro Channel
Architecture, and device driver software for AIX on the RS/6000.
	Both papers focus on the key architectural issues and the
design tradeoffs necessary to achieve high performance.  Both use
custom hardware to implement data transfer and ATM cell formatting in
the transmit and receive directions.  Davie's design includes two
microprocessors with firmware to handle the segmentation and
reassembly algorithms, while Traw and Smith use dedicated hardware.
	Those who have implemented host interfaces have frequently
found that the nondeterministic behavior of the receiver section makes
it the most problematic part of an interface to implement. The paper
by Moors and Cantoni addresses a wide range of issues associated with
receiver implementation for ATM host interfaces, including reassembly,
buffer allocation, scheduling, and connection management. This paper
is likely to be most useful to future interface implementors.
	We have included two papers which specifically address the
issues of host interface architectural support for multimedia traffic.
	The paper by Blair, Campbell, Coulson, Garcia, Scott,
Hutchison and Shepherd, "Supporting Continuous Media in Heterogeneous
Distributed Systems Through a Multimedia Network Interface" presents
some of these issues. The approach taken by the authors is to build an
experimental prototype for a multimedia network interface.  This
interface handles all of the real time aspects of multimedia streams.
Of particular interest is the use of dedicated off-board processors
and their specialization for this interface by a standalone real time
Occam language kernel.
	The paper by Richard, Costa and Sato, "The Washington
Broadband Terminal" examines the issues in constructing interfaces
that handle video and audio.  They report on equipment that has been
built and is in use at Washington University, St Louis.
	Some themes emerge from this issue.  Two important ones are
partitioning of functionality and the nature of the path, usually a
bus, between the computer and what we call the host interface.
	Traditionally, computer/network interface functionality was
implemented in software operating on the host processor, or by using a
special front-end processor.  The six orders of magnitude increase in
transmission rate from Kb/s to Gb/s over two decades requires
fundamental examination of computer/network interface design.  On one
hand it has become clear that there are advantages in performing time
critical functions which are potential bottlenecks in hardware.
However, it is also clear that not everything can be performed using
special hardware, either due to a need for flexibility, the inherent
complexity of the task, or the rarity with which it is performed.  For
example, functions like network management and fault prevention and
recovery will continue to be performed in software.  Thus, some of the
principle questions confronting network interface designers are:

 (1) How to partition between hardware and software functions.
 (2) Where to perform the software functions --- special processors or at the
     host?
 (3) What are the consequences of the high-speed computer/network
     interfaces on the protocol stack; put the other way round, does
     the traditional layered structure of protocol architecture
     facilitate the construction of efficient and cost effective
     computer/network interfaces?

Another recurrent theme emerging from the literature on host
interfacing is that the networking performance seen by applications
continues to be limited by factors that are intrinsic to the
workstation design, not the interface design. In general, host
interfaces designers must work with the general purpose I/O busses
that workstation designers provide. In some cases, the bandwidth
available across these busses is simply inadequate; in others, the way
in which the bus permits access to the host causes some other
subsystem, such as the main memory or the bus controller, to become a
bottleneck. When busses require attached devices to perform DMA to
achieve reasonable speed, overall throughput may suffer if the DMA
ultimately results in an extra data copy. All of these issues could be
resolved if host interfaces were considered as integral parts of the
host, rather than post-design add-ons. Those with an interest in high
performance networking can only hope that the importance of host
interface design will be increasingly recognized by the designers of
host computers.
	It is clear from many of these papers that the network
interface need not be the bottleneck in high-speed network
communication.  It is equally clear that off-the-shelf workstation
hardware and software are outmatched by networks of this speed.  At
the hardware level, the I/O buses and memory systems raise obstacles,
and in the operating system software, the layered protocol
implementations and multiple data copies are suboptimal.  Since
research prototypes have addressed each of these shortcomings, it is
to be hoped that well-balanced, high-performance network workstations
are now within sight.
	In this issue we see a continuum of views on which functions
are performed by host interface and which by the host.  We have
articles which make pleas for minimal host interfaces and others which
describe systems where the host is merely a management entity
controlling the resources of the interface.  This tension may suggest
to some that treating networks as first class devices within
workstations may not be going far enough; our entire concept of
processor-centric bus architectures may be subject to a great deal of
scrutiny over the next few years.
	This special issue does not provide all the answers but rather
gives a snapshot of the activities in these dynamic and intriguing
aspects of high-speed computing and networking.
	There are a number of key questions which we see as remaining
unanswered, and hence ripe for investigation in the future. First, it
is clear that almost all of the results reported here are
environment-specific, e.g., depending on specific computers,
applications, or packet characteristics.  This begs for a set of
design rules based on characterizations of the environment. Second,
the results reported here are for the most part results based on
workstation-class machines. How do other machine classes affect the
design of host/network interfaces?
	For example, modern supercomputer-class machines have enormous
memory bandwidths, removing a significant constraint on workstation
architectures. On the other hand, the tradeoffs are altered, as
devoting ten percent of a workstation's capacity to networking seems
an acceptable tradeoff, while ten percent of a supercomputer is a
rather more expensive commodity.
	Another key machine class are massively parallel machines
composed of small processors.  These machines offer tremendous
aggregate memory bandwidths and processing capabilities, and leads to
the question of scalable host interfacing architectures based on
parallelism, e.g., host interface adaptors which attach to a plane of
a hypercube or the edge of a mesh. Simple hardware can easily be
devised, but the test of the designer is delivery of performance to
applications, and this will require much more research.
	Finally, the reported results have focussed mainly on
lower-level issues, such as process-adapter latencies and transfer
rates. It is likely that as new applications strain existing
architectures and exercise unexpected bottlenecks, new architectures
will arise to exorcise these performance problems as well.
	This issue would not exist without the careful readings and
judgements of a considerable number of technical reviewers, whom we
have enumerated following this editorial. They, perhaps more than
anyone, ensure the quality of the material found here. Special thanks
go to Dr. W. David Sincoskie of Bellcore and Dr. Nicholas F. Maxemchuk,
IEEE JSAC Senior Editors, and Sue McDonald of Bellcore, on the JSAC
Editorial Board.

							Jonathan  M. Smith
							Eric C. Cooper
							Bruce S. Davie
							Ian M. Leslie
							Yoram Ofek
							Richard Watson