Lab 0 - Getting Started

CSE 372 (Spring 2008): Computer Organization and Design Lab

Due Friday, Feburary 8th (writeup and demo in KLab by 7pm)

This lab should be done individually.

This lab is worth 10 points.

Instructions

Before you begin, you'll want to walk through the tutorial.

In this lab, you'll be reverse-engineering a mystery FPGA configuration. The mystery configuration contains a simple combinational logic function of four inputs and four outputs. The four inputs are switches 0, 1, 2, and 3 on component SW7 (the switches under the open rectangle on the lower left). The outputs are LEDs 0-3 (right next to them).

Your task is to figure out what function this configuration implements (by recording the outputs for all eight possible switch settings) and then write a simple structural Verilog file that implements the exact same function. To load the config file, you'll need to run iMPACT from the Windows Start menu. Once loaded, record the operation of the circuit. Next, follow the Verilog entry instructions from the tutorial, but include in the Verilog file the required logic gates and any need wires. For an example of structural Verilog, see the two "HDL" slides from lectures notes from the first day of class. The simple gates available are: not, and, or, nand, nor, and xor.

Important

In this lab you can only use structural Verilog and only these six gate types: not, and, or, nand, nor, and xor

Note

The LED outputs and the switches are both use "active low" signaling. That is, the LED turns on when its signal is a 0 and the LED is off when its signal is a 1. Similarly, The switches return a 1 when off and a 0 when on. This can be ultra-confusing until you get used to it. You'll need to take this into account when writing your Verilog.

Demo

When you've completed and tested your design, demo your design to one of the TAs. They will verify the design works correctly and ask you a few questions about the design. If you pass the demo, they will check you off.

What to Turn In

Turn in the follow items in class:

A table that shows the input and output of the mystery function
A printout of your Verilog code
Answers to the following questions:
1. What high-level operation does this function perform?
2. What problems (if any) did you encounter while doing this lab?

Addendum

A few hints:

In Verilog, various gates (such as and, or, nand, nor) can take multiple inputs. For example, to calculate the "or" of three signals in Verilog:
```
or (out, in1, in2, in3)
```
One systematic way to make any combinational logic function is to build a PLA (which were discussed in CSE240). Remember, a PLA has an "and" term for each "one" output in the function. These "and" terms are the "and" of each of the inputs or its inverse. The final answer is the "or " of these "and" terms.