Papers by Andre' DeHon

Reconfigurable Computing/FPGA Papers (and Molecular Electronics)

IETCDT2009: Benjamin Gojman, Harika Manem, Garret S. Rose, and André DeHon. Inversion Schemes for Sublithographic Programmable Logic Arrays In IET Computers and Digital Techniques, Volume 3, Number 6, Pages 525--642, November, 2009. [abstract and IEEE link].
FPT2009a: Benjamin Gojman and André DeHon. VMATCH: Using Logical Variation to Counteract Physical Variation in Bottom-Up, Nanoscale Systems. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2009. [Abstract and Paper Links]
FPT2009b: Nachiket Kapre and André DeHon. Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs. In Proceedings of the IEEE International Conference on Field-Programmable Technology, December, 2009. [Abstract and Paper Links]
FPL2009: Nachiket Kapre and André DeHon. Performance Comparison of Single-Precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core Processors. In Proceedings of the International Conference on Field Programmable Logic and Applications, September, 2009. [Abstract and Paper Links]
FCCM2009: Nachiket Kapre and André DeHon. Accelerating SPICE Model-Evaluation using FPGAs. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2009. [Abstract and Paper Links]
TRVLSI2009: Helia Naeimi and André DeHon. Fault Secure Encoder and Decoder for NanoMemory Applications. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 17, Number 4, Pages 473--486, April 2009. [abstract and IEEE link].
FPGA2009: Raphael Rubin and André DeHon. Choose-Your-Own-Adventure Routing: Lightweight Load-Time Defect Avoidance. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 23--32, February, 2009. [Abstract and Paper Link]
TC2009: Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, and André DeHon. Pipelining Saturated Accumulation. In IEEE Transactions on Computers, Volume 58, Number 2, pp. 208--219, February, 2009. [Abstract and Paper Link]
NDCS2008: André DeHon. The Case for Reconfigurable Components with Logic Scrubbing: Regular Hygiene Keeps Logic FIT (low). In Proceedings of the IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems (NDCS2008), September 2008. [Abstract and Paper Links]
NANOTECHNOLOGY2008: Helia Naeimi and André DeHon. Fault-Tolerant Sub-lithographic Design with Rollback Recovery. In Nanotechnology, Volume 19, Number 11, Article 115708, March 19, 2008. [Abstract and Paper Links]
NANONETS2007: Helia Naeimi and André DeHon. Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder. In Proceedings of the International Conference on Nano-Networks (Nanonets2007), September 2007. [Abstract and Paper Links]
DFT2007: Helia Naeimi and André DeHon. Fault Secure Encoder and Decoder for Memory Applications. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS2007), September 2007. [Abstract and Paper Links]
ARITH2007: Nachiket Kapre and André DeHon. Optimistic Parallelization of Floating-Point Accumulation. In Proceedings of the IEEE Symposium on Computer Arithmetic (ARITH18), pp. 205--213, June 2007. [Abstract and Paper Links]
NANONETS2006b: Benjamin Gojman, Raphael Rubin, Concetta Pilotto, Tetsufumi Tanamoto, and André DeHon. 3D Nanowire-Based Programmable Logic. In Proceedings of the International Conference on Nano-Networks (Nanonets2006), September 2006. [Abstract and Paper Links]
NANONETS2006a: Kumiko Numora, Keiko Abe, Shinobu Fujita, and André DeHon. Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. In Proceedings of the International Conference on Nano-Networks (Nanonets2006), September 2006. [Abstract and Paper Links]
JETC2006: John E. Savage, Eric Rachlin, André DeHon, Charles M. Lieber, and Yue Wu. Radial Addressing of Nanowires. In ACM Journal on Emerging Technologies in Computing Systems, Volume 2, Number 2, Pages 129--154, April 2006. [abstract and ACM Link].
JMM2006a: André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, and John Wawrzynek. Stream Computations Organized for Reconfigurable Execution. In Journal of Microprocessors and Microsystems, Volume 30, Number 6, Pages 334--354, September, 2006. [Abstract and DOI Link]
JMM2006b: André DeHon, Randy Huang, and John Wawrzynek. Stochastic Spatial Routing for Reconfigurable Networks. In Journal of Microprocessors and Microsystems, Volume 30, Number 6, Pages 301--318, September, 2006. [Abstract and DOI Link]
FCCM2006a: Michael deLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomas Uribe, Thomas F. Knight, Jr. and André DeHon. GraphStep: A System Architecture for Sparse-Graph Algorithms. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2006. [Abstract and Paper Links]
FCCM2006b: Nachiket Kapre, Nikil Mehta, Michael deLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael Wrighton, and André DeHon. Packet-Switched vs. Time-Multiplexed FPGA Overlay Networks. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2006. [Abstract and Paper Links]
ASPDAC2006: Michael Wrighton and André DeHon. SAT-Based Optimal Hypergraph Partitioning with Replication. In Proceedings of the Asia and South Pacific Design Automation Conference, January 2006. [abstract and paper links].
ICFPT2005: Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, and André DeHon. Pipelining Saturated Accumulation. In Proceedings of the International Conference on Field-Programmable Technology, December, 2005. [abstract and paper links].
TNANO2005b: André DeHon. Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches. In IEEE Transactions on Nanotechnology, Volume 4, Number 6, Pages 681--687, Nov. 2005. [abstract and IEEE link].
JETC2005: André DeHon. Nanowire-Based Programmable Architectures. In ACM Journal on Emerging Technologies in Computing Systems, Volume 1, Number 2, Pages 109--162, July 2005. [abstract and ACM Link].
IEEEDT2005: André DeHon and Helia Naeimi. Seven Strategies for Tolerating Highly Defective Fabrication. In IEEE Design and Test of Computers, Volume 22, Number 4, Pages 306--315, July-August 2005. [abstract].
TNANO2005a: André DeHon, Seth Copen Goldstein, Philip J. Kuekes, and Patrick Lincoln. Non-Photolithographic Nanoscale Memory Density Prospects. In IEEE Transactions on Nanotechnology, Volume 4, Number 2, Pages 215--228, March 2005. [abstract and IEEE link].
FPGA2005a: André DeHon. Design of Programmable Interconnect for Sublithographic Programmable Logic Arrays. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 127--137,February, 2005. [abstract, paper, and slide links].
FPGA2005b: Michael deLorimier and André DeHon. Floating-Point Sparse Matrix-Vector Multiply for FPGAs. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 75--85, February, 2005. [abstract, paper, and slide links].
ICFPT2004: Helia Naeimi and André DeHon. A Greedy Algorithm for Tolerating Defective Crosspoints in NanoPLA Design. In Proceedings of the International Conference on Field-Programmable Technology, pages 49--56, December, 2004. [abstract and paper links].
TRVLSI2004a: André DeHon and Raphael Rubin. Design of FPGA Interconnect for Multilevel Metalization. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Number 10, Pages 1038--1050, October 2004. [abstract and IEEE link].
TRVLSI2004b: André DeHon. Unifying Mesh- and Tree-Based Programmable Interconnect In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Number 10, Pages 1051--1065, October 2004. [abstract and IEEE link].
LLNSD2004: André DeHon. Law of Large Numbers System Design. In Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, pp. 213--241, Kluwer, 2004. [abstract].
FCCM2004: André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael Vanier, and Michael Wrighton. Design Patterns for Reconfigurable Computing. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2004. [abstract and paper link].
FPGA2004: André DeHon and Michael J. Wilson. Nanowire-Based Sublithographic Programmable Logic Arrays. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 123--132, February, 2004. [abstract, paper, and slide links].
TNANO2003: André DeHon, Patrick Lincoln, and John E. Savage. Stochastic Assembly of Sublithographic Nanoscale Interfaces. In IEEE Transactions on Nanotechnology, Volume 2, Number 3, Pages 165--174, September 2003. [abstract and IEEE link].
HOTCHIPS2003: André DeHon with Charles M. Lieber, Patrick Lincoln, and John E. Savage. Sub-lithographic Semiconductor Computing Systems. In Hot Chips Symposium 2003, August 17--19, 2003. [abstract, paper, slides].
TNANO2003: André DeHon. Array-Based Architecture for FET-Based, Nanoscale Electronics. In IEEE Transactions on Nanotechnology, Volume 2, Number 1, Pages 23--32, Mar 2003. [abstract and IEEE link].
FPGA2003a: Raphael Rubin and André DeHon. Design of FPGA Interconnect for Multilevel Metalization. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 154--163, February, 2003. [abstract, paper, and slide links].
FPGA2003b: Michael Wrighton and André DeHon. Hardware-Assisted Simulated Annealing with Application for Fast FPGA Placement. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 33--42, February, 2003. [abstract, paper, and slide links].
FPGA2003c: Randy Huang, John Wawrzynek, and André DeHon. Stochastic, Spatial Routing for Hypergraphs, Trees, and Meshes. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 78--87, February, 2003. [abstract, paper, and slide links].
ICCAD2002: Michael Butts, André DeHon, and Seth Copen Goldstein, Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips. In Proceedings of the International Conference on Computer-Aided Design, pages 433--440, November, 2002. [abstract, paper, and slide links].
UMC2002: André DeHon. Very Large Scale Spatial Computing. In Proceedings of the Third International Conference on Unconventional Models of Computation, pages 27--37, October 2002. [abstract, paper, and slide links].
FCCM2002: André DeHon, Randy Huang, and John Wawrzynek. Hardware-Assisted Fast Routing. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 205--215, April 2002. [abstract, paper, and slide links].
NSC2002: André DeHon. Array-Based Architecture for Molecular Electronics. In Proceedings of the First Workshop on Non-Silicon Computation, February 2002. [abstract, paper, and slide links].
FPGA2002: Yury Markovskiy, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, and André DeHon. Analysis of QuasiStatic Scheduling Techniques in a Virtualized Reconfigurable Machine. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 196--205, February 2002. [abstract, paper, and slide links].
MSP2001: Eylon Caspi, Randy Huang, Yury Markovskiy, Joseph Yeh, John Wawrzynek, and André DeHon. A Streaming Multi-Threaded Model. In Third Workshop on Media and Stream Processing (MSP-3), December 2, 2001, [abstract, paper links].
SLIP2001: André DeHon. Rent's Rule Based Switching Requirements. In System-Level Interconnect Prediction (SLIP 2001), pages 197--204, March 31--April 1, 2001, [abstract, paper links].
FPL2000: Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, and André DeHon. Stream Computations Organized for Reconfigurable Execution (SCORE): Extended Abstract. In Conference on Field Programmable Logic and Applications (FPL '2000), pages 605--614, August 28--30, 2000. [abstract, paper links].
SPAA2000: André DeHon. Compact, Multilayer Layout for Butterfly Fat-Tree. In Twelfth Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2000), pages 206--215, July 9-12, 2000. [abstract, paper links].
Computer2000: André DeHon. The Density Advantage of Configurable Computing. IEEE Computer, 33(4):41--49, April 2000. [abstract and paper link]
DAC99: André DeHon, John Wawrzynek. Reconfigurable Computing: What, Why, and Design Automation Requirements? In Proceedings of the 1999 Design Automation Conference, pages 610--615, June 1999. [abstract, paper, and slide links].
VLSI99: Stylianos Perissakis, Yangsung Joo, Jinhong Ahn, André DeHon, and John Wawrzynek. Embedded DRAM for a Reconfigurable Array. In Proceedings of the 1999 Symposium on VLSI Circuits, June 1999. [abstract, paper, and slide links].
FPGA99a: André DeHon. Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why you don't really want 100% LUT utilization). In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 125--134, February 1999. [abstract, paper, and slide links].
FPGA99b: William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, Varghese George, John Wawrzynek, André DeHon. HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 69--78, February 1999. [abstract, paper, and slide links].
ISSCC99: Andre DeHon, Trends toward Spatial Computing Architectures. In ISSCC Digest of Technical Papers, pages 362--363. IEEE, February 1999. [abstract, paper, and slide links].
SPIE98: André DeHon. Comparing Computing Machines. In Configurable Computing: Technology and Applications, Proceedings of SPIE 3526, p. 124, November 1998. [abstract, paper, and slide links]
FCCM98: Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, and John Wawrzynek. Object Oriented Circuit-Generators in Java. In Proceedings of the IEEE Symposium on Field-Programmable Gate Arrays for Custom Computing Machines. IEEE, IEEE, April 1998. [abstract and paper links]
FPGA98: Timothy Callahan, Philip Chong, André DeHon, and John Wawrzynek. Fast Module Mapping and Placement for Datapaths in FPGAs. In Proceedings of the International Symposium on Field Programmable Gate Arrays, February 1998. [Abstract and paper].
HICSS97: William H. Mangione-Smith, Brad Hutchings, David Andrews, André DeHon, Carl Ebeling, Reiner Hartenstein, Oskar Mencer, John Morris, Krishna Palem, Viktor K. Prasanna, and Henk A. E. Spaanenburg. Seeking Solutions in Configurable Computing. IEEE Computer, 30(12):38--43, December 1997. [PDF]
HC97: Ethan Mirsky and André DeHon. MATRIX: A Reconfigurable Computing Device with Configurable Instruction Distribution and Deployable Resources. In Hot Chips Symposium 1997, 1997. [abstract, paper, and slides links].
FPD96: André DeHon. Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density. In Proceedings of the Fourth Canadian Workshop on Field-Programmable Devices, pages 47-54, May 1996. [abstract, paper, and slide links].
FCCM96: Ethan Mirsky and Andre DeHon. MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April 1996. [abstract, paper, and slide links].
FPGA96a: Andre DeHon. DPGA Utilization and Application. In Proceedings of the 1996 International Symposium on Field Programmable Gate Arrays. ACM/SIGDA, February 1996. [abstract, paper, and slide links].
FPGA96b: Andre DeHon. Entropy, Counting, and Programmable Interconnect. In Proceedings of the 1996 International Symposium on Field Programmable Gate Arrays. ACM/SIGDA, February 1996. [abstract, paper, and slide links].
FPD95: Edward Tau, Ian Eslick, Derrick Chen, Jeremy Brown, and Andre DeHon. A First Generation DPGA Implementation. In Proceedings of the Third Canadian Workshop on Field-Programmable Devices, pages 138-143, May 1995. [abstract, paper, slides link].
FCCM94: Andre DeHon. DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April 1994. [abstract, paper link].
FPGA94: Michael Bolotski, Andre DeHon, and Thomas F. Knight, Jr. Unifying FPGAs and SIMD Arrays. In FPGA Workshop, 1994. proceedings not available outside of the workshop [abstract, paper, slide links].

Multiprocessor Interconnect Papers

VLSIDESIGN98: André DeHon and Thomas F. Knight Jr. High Performance Point-to-Point Transmission Line Signaling. VLSI Design, 7(1):111--129, 1998. [PDF] [PS]
IJHSES95: André DeHon, Fred Drenckhahn, Thomas F Knight Jr., and Henry Minsky. Three-Dimensional Packaging for High-Performance Interconnect in Large-Scale VLSI Systems. International Journal of High Speed Electronics and Systems, 6(4):613--630, 1995.
ITC94: Andre DeHon. In-System Timing Extraction and Control through Scan-Based, Test-Access Ports. In Proceedings of the International Test Conference, pages 350-359, 205 Tennyson Avenue, Suite C, Altoona, PA 16602, October 1994. IEEE, International Test Conference. [PS link].
ISCA94: Andre DeHon, Frederic Chong, Matthew Becker, Eran Egozy, Henry Minsky, Samuel Peretz, and Thomas F. Knight, Jr. METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks. In Proceedings of the International Symposium on Computer Architecture, pages 266-277, May 1994. [abstract, paper links].
ISSCC93: Andre DeHon, Thomas F. Knight Jr., and Thomas Simon. Automatic Impedance Control. In ISSCC Digest of Technical Papers, pages 164-165. IEEE, February 1993. [PS link].
DFT92: Andre DeHon. Scan-Based Testability for Fault-tolerant Architectures. In Duncan M. Walker and Fabrizio Lombardi, editors, Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pages 90-99. IEEE, IEEE Computer Society Press, 1992. [PDF] [PS]
ARVLSI92: Frederic Chong, Eran Egozy, and Andre DeHon. Fault Tolerance and Performance of Multipath Multistage Interconnection Networks. In Thomas F. Knight Jr. and John Savage, editors, Advanced Research in VLSI and Parallel Systems 1992, pages 227-242. MIT Press, March 1992. [PDF] [PS]
ISSMM91: Andre DeHon, Thomas F. Knight Jr., and Henry Minsky. Fault-Tolerant Design for Multistage Routing Networks. In International Symposium on Shared Memory Multiprocessing, pages 60-71. Information Processing Society of Japan, April 1991. [PDF (having problems with)] [PS]
HotChips91: Henry Minsky, Andre DeHon, and Thomas F. Knight Jr. RN1: Low-Latency, Dilated, Crossbar Router. In Hot Chips Symposium III, 1991. [PS link].
ARVLSI91: Andre DeHon. Practical Schemes for Fat-Tree Network Construction. In Carlo H. Sequin, editor, Advanced Research in VLSI: International Conference 1991, pages 307-322. MIT Press, March 1991. [PDF] [PS]

André DeHon