How do we physically implement computations?
Broadly, my research interests address this question, including
physical substrates (VLSI, molecular, ...), programmable media
(FPGAs, (multi-) processors, ...), mapping (compilation and CAD),
system abstractions and dynamic management
(run-time systems, OS, scheduling),
and problem capture (programming languages).
- Chair of ACM SIGDA TC-FPGA -- Checkout our new web portal and wiki.
- FCCM20 papers have been identified. See
for list of papers and endorsements.
FPGA20 papers have been identified. See
FPGA20 page for
list of papers and endorsements.
Underpinnings of Reconfigurable Computing Architectures in Proc. of the IEEE Special Issue on Reconfigurable Sysems,
- Reconfigurable Computing Architectures in Proc. of the IEEE Special Issue on Reconfigurable Sysems,
Support for Software-Defined Metadata Processing in ASPLOS, March 2015.
of Memory Architecture on FPGA Energy Consumption
in FPGA, February 2015.
Near-Associative Memories on FPGAs in ACM TRETS, January 2015.
- GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays using Timing Extraction
in ACM TRETS, December 2014.
Router Support for Endpoint-Authorized Decentralized Traffic Filtering to
Prevent DoS Attacks. in ICFPT, December 2014.
- Kung Fu Data Energy---Minimizing Communication Energy in FPGA Computations in FCCM, May 2014.
- Energy Reduction through Differential Reliability and Lightweight Checking in FCCM, May 2014.
- GROK-INT: Generating Real On-chip Knowledge for Interconnect Delays Using Timing Extraction in FCCM, May 2014.
- A Verified
Information-Flow Architecture in POPL, January 2014.
- Exploiting Partially Defective LUTs: Why You Don't Need Perfect Fabrication
in ICFPT, December,
2013. (Outstanding Paper Award)
- Low-Fat Pointers: Compact Encoding and Efficient Gate-Level Implementation
of Fat Pointers for Spatial Safety and Capability-based Security
in CCS, November 2013.
Parallel Floating-Point Accumulation. in ARITH, April 2013.
- Hardware Support for Safety Interlocks and
Introspection in SASO
Adaptive Host and Network Security
Workshop, Sept. 14, 2012
Study of Energy & Delay Benefits of Component-Specific Routing in
Spatial Processors Interconnected for Concurrent
Execution for Accelerating the SPICE Circuit Simulator Using an
FPGA in IEEE Tr. on Computer-Aided Desgin of Integrated
Circuits and Systems, January 2012.
- Final Report of
the CRA/CCC Visioning study on Cross
Layer Reliability, March 2011
- Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, edited book from Elsevier (available from amazon.com)
- For earlier publications, see longer list.
- ESE370: Circuit-Level
Modeling, Design, and Optimization for Digital Systems, (Penn, Fall
2010, 2011, 2012, 2013, 2014)
- ESE534: Computer
Organization, (Penn, Spring 2010, 2012,2014)
- ESE250: Digital Audio
Basics, (Penn, Fall 2009, Spring 2013)
- ESE535: Electronic Design
Automation (Penn, Spring 2008, 2009, 2011, 2013, 2015)
- see longer list for earlier courses
André DeHon <firstname.lastname@example.org>
Electrical and Systems Engineering
University of Pennsylvania
200 S. 33rd Street
Philadelphia, PA 19104