André DeHon <andre@acm.org> Associate Professor Electrical and System Engineering Computer and Information Science (secondary) University of Pennsylvania Chair of Computer Engineering Program Committee Office: Moore GRW 262 Office Hour: T4:30-5:30pm (Spring 2011)

IC Group (research page) Lab: Moore 315

Research

Broadly, my research interests address this question, including physical substrates (VLSI, molecular, ...), programmable media (FPGAs, (multi-) processors, ...), mapping (compilation and CAD), system abstractions and dynamic management (run-time systems, OS, scheduling), and problem capture (programming languages).

Ongoing

• Chair of ACM SIGDA TC-FPGA -- Checkout our new web portal.
  • nominate significant papers from the first 20 years of FCCM for FCCM20
  • nominations for FPGA20 have closed. Watch FPGA 2012 for the results.

Recent

• Limit Study of Energy & Delay Benefits of Component-Specific Routing in FPGA 2012.
• SPICE²: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA in IEEE Tr. on Computer-Aided Desgin of Integrated Circuits and Systems, January 2012.
• Choose-Your-Own-Adventure Routing: Lightweight Load-Time Defect Avoidance. in ACM TRETS, December 2011.
• VLIW-SCORE: Beyond C for Sequential Control of SPICE FPGA Acceleration in ICFPT, December 2011.
• Spatial hardware implementation for sparse graph algorithms in GraphStep in ACM TAAS, September 2011.
• Preliminary Design of the SAFE Platform in PLOS, October 2011.
• Final Report of the CRA/CCC Visioning study on Cross Layer Reliability, March 2011
• An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads in IJRC, March 2011.
• Timing-Driven Pathfinder Pathology and Remediation: Quantifying and Reducing Delay Noise in VPR-Pathfinder in FPGA 2011.
• Crystals and Snowflakes: Building Computation from Nanowire Crossbars in IEEE Computer, February 2011.
• Inversion Schemes for Sublithographic Programmable Logic Arrays in IET Computers and Digital Techniques, November 2009.
• VMATCH: Using Logical Variation to Counteract Physical Variation in Bottom-Up, Nanoscale Systems in ICFPT 2009
• Fault Secure Encoder and Decoder for NanoMemory Applications, in IEEE Tr. on VLSI Systems, April 2009.
• Pipelining Saturated Accumulation in IEEE Tr. on Computers, February 2009
• Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, edited book from Elsevier (available from amazon.com)
• For earlier publications, see longer list.

Courses

• ESE534: Computer Organization, Spring 2012

• ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems, (Penn, Fall 2010, 2011)
• ESE534: Computer Organization, (Penn, Spring 2010)
• ESE250: Digital Audio Basics, (Penn, Fall 2009)
• ESE535: Electronic Design Automation (Penn, Spring 2008, 2009, 2011)
• see longer list for earlier courses

Writing

• Unified publication list
• Selected Themes:
  • Molecular-scale/Sublithographic Architecture
  • Interconnect
  • Compute Models and Design Patterns
  • MATRIX
  • DPGA
• Theses
• Assorted advice, reflections, recommended reading

Academic History

• CALTECH Assistant Professor of Computer Science 1999--2006
• UCB Postdoc 1996-1999
• MIT SB '90, SM '93, PhD '96
• LSMSA '86 [Alumni]