Research
How do we physically implement computations?
Broadly, my research interests address this question, including
physical substrates (VLSI, molecular, ...), programmable media
(FPGAs, (multi-) processors, ...), mapping (compilation and CAD),
system abstractions and dynamic management
(run-time systems, OS, scheduling),
and problem capture (programming languages).
Ongoing
- Chair of ACM SIGDA TC-FPGA -- Checkout our new web portal and wiki.
- FCCM20 papers have been identified. See
FCCM20
for list of papers and endorsements.
-
FPGA20 papers have been identified. See
FPGA20 page for
list of papers and endorsements.
Recent
- Accurate
Parallel Floating-Point Accumulation. in ARITH, April 2013.
- Location,
Location, Location---The Role of Spatial Locality in Asymptotic Energy
Minimization in
FPGA, February 2013.
- Area-Efficient
Near-Associative Memories on FPGAs in FPGA, February 2013.
- GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays using Timing Extraction in
FPGA, February 2013.
- FPGA
Optimized Packet-Switched NoC using Split and Merge Primitives in ICFPT, December 2012.
- Hardware Support for Safety Interlocks and
Introspection in SASO
Adaptive Host and Network Security
Workshop, Sept. 14, 2012
- Limit
Study of Energy & Delay Benefits of Component-Specific Routing in
FPGA 2012.
- SPICE2:
Spatial Processors Interconnected for Concurrent
Execution for Accelerating the SPICE Circuit Simulator Using an
FPGA in IEEE Tr. on Computer-Aided Desgin of Integrated
Circuits and Systems, January 2012.
- Choose-Your-Own-Adventure
Routing: Lightweight Load-Time Defect
Avoidance. in ACM TRETS, December 2011.
-
VLIW-SCORE: Beyond C for Sequential Control of SPICE FPGA Acceleration
in ICFPT, December 2011.
-
Spatial
hardware implementation for sparse graph algorithms in GraphStep in
ACM TAAS, September 2011.
- Preliminary Design of the
SAFE Platform in PLOS, October 2011.
- Final Report of
the CRA/CCC Visioning study on Cross
Layer Reliability, March 2011
- An NoC
Traffic Compiler for Efficient FPGA Implementation of Sparse
Graph-Oriented Workloads in IJRC, March 2011.
- Timing-Driven
Pathfinder Pathology and Remediation: Quantifying and Reducing Delay
Noise in VPR-Pathfinder
in FPGA 2011.
-
Crystals and Snowflakes: Building Computation from Nanowire Crossbars
in IEEE
Computer, February 2011.
- Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, edited book from Elsevier (available from amazon.com)
- For earlier publications, see longer list.
Courses
Current
Past
- ESE370: Circuit-Level
Modeling, Design, and Optimization for Digital Systems, (Penn, Fall
2010, 2011, 2012)
- ESE534: Computer
Organization, (Penn, Spring 2010, 2012)
- ESE250: Digital Audio
Basics, (Penn, Fall 2009)
- ESE535: Electronic Design
Automation (Penn, Spring 2008, 2009, 2011)
- see longer list for earlier courses
Writing
Academic History
André DeHon <andre@acm.org>
Electrical and Systems Engineering
University of Pennsylvania
200 S. 33rd Street
Philadelphia, PA 19104
GPG Key
