Amir Roth Associate Professor Department of Computer and Information Science University of Pennsylvania email: amir (you can figure out the domain name from the url) phone: 215.573.0175 office: 603 Levine hours: M 10:30-12, T 1:30-3, or by appointment

• Dataflow mini-graphs are compound multi-operation instructions with the interfaces of singleton RISC instructions: atomic execution units with at most two register inputs, one register output, one memory reference, and one control transfer. A static rewriting tool replaces frequently occurring dataflow graphs that meet mini-graph interface specifications with "handles", quasi-instructions that encode the mini-graph's register interface and an index to its internal definition. A mini-graph processor treats handles as singleton instructions at all pipeline stages except for execution, where it expands them to their constituent instructions using a technique that resembles table-driven micro-code. Mini-graphs amplify the capacity and bandwidth of superscalar processors, allowing a 4-way issue machine to perform like a 6-way issue machine.
  
  
• The ONCore project looks at new designs for large memory latency-tolerant superscalar instruction windows. The two challenges of building large windows are managing the physical complexity of the structures and interconnects and overcoming branch mispredictions which limit the utility of the window. We meet these challenges not by stepping outside the superscalar paradigm but by redesigning key algorithms and structures within the paradigm. One of our early successes has been with the in-flight load/store unit (i.e., the load/store queue) and the store-load forwarding and memory-dependence violation detection algorithms. We have a design for an in-flight load/store unit that implements both pieces of functionality without associative search. For store-load forwarding, we use a memory-dependence predictor to predict for each dynamic load the single most-likely-to-forward store instance. Load execution doesn't search the store queue, but makes an indexed read at exactly one position. Surprisingly (or not, depending on who you ask) store queue indices can be predicted with 99.9% accuracies. For memory-dependence violation detection, we use in-order load re-execution prior to commit, which also serves as the speculative indexed forwarding verification mechanism. A re-execution filter called store vulnerability window (SVW) means that for correctness, only 2-3% of all loads have to re-execute. This project is a collaboration with Prof. Milo Martin.
  
  
• RENO is a modified MIPS R10000 register renaming circuit that applies the dynamic counterparts of certain static compiler optimizations to the dynamic instruction stream.
  
  

• Pre-execution is a paradigm for extracting ILP from general purpose integer programs. Pre-execution removes stalls due to cache misses and mis-predicted branches by speculatively executing computations of likely-to-miss loads and likely-to-mispredict branches on separate threads, then passing the results back to the main thread. My PhD thesis described Speculative Data-Driven Multithreading (DDMT), one of the first proposed implementations of pre-execution. I am currently working on developing tools and techniques for measuring the performance potential of pre-execution and for automating pre-execution thread (p-thread) construction.
  
  
• Dynamic Instruction Stream Editor (DISE) is a programmable instruction macro-expander, similar in structure to the X86 CISC-to-RISC translator except it modifies instruction functionality rather than instruction granularity. DISE is an implementation vehicle for application customization functions like compression, fault detection and isolation, profiling, debugging, and security. The DISE project is a collaboration with professor E Lewis.
  
  

These projects are just some of the things we are doing at Penn's Architecture and Compilers Group (ACG). Please visit the group page for more information.

The Pips
I (attempt to) advise three PhD students:

• Cyberanna (6th year, currently ABD at Intel MRL in Santa Clara/Church of the Epiphany)
• T2 (4th year, currently made of liquid metal)
• Paris (3rd year, currently starring in "The Simple Life II" with Nicole Richie)

• The impaler (currently impaling at Google in Manhattan)