In this lab you will use the components you built in the previous lab to create a single cycle implementation for a subset of the R372 instruction set. Your processor should support all instructions except for MULR, LCTR, and CCTR. Your processor will be tested on four programs, and not all programs use all instructions. Therefore, it is better to have a processor that executes a subset of the instructions correctly than one that executes no instruction correctly.

Interface

The processor you will design will act like a single-program computer with a very simple external interface. The component name will be r372_sc. It will have the following interface:

• 1-bit input signal clk.
• 1-bit input signal rst. When rst asserted, the processor resets the program counter to 0. It begins executing as soon as the rst signal is de-asserted.
• 1-bit output signal halt This signal asserts whenever the processor encounters either the HALT instruction or any of the undefined instructions. When this signal asserts, the processor write-disables the PC and essentially stops until the next assert of rst.

Structural Specifications and Hints

A processor consists of a datapath and a controller. In the first three labs, you have written most of the datapath components you will need: muxes, decoders, an ALU, a barrel shifter, a register file, and memory modules. You will use structural Verilog to put these components together into an R372 datapath. There are many ways to put the datapath together and all of them are right as long as they work. Design the datapath as you wish. If you didn't get parts of the first three labs working, you can use the solution code in ~amir/cse371/labs/{lab1.solutions|lab2.solutions|lab3.solutions|common}/ instead. I prefer that you use your own code if possible.

A controller for a single-cycle datapath takes the current opcode as input and outputs control signals. Remember, control signals in general come in two flavors: mux selectors, and write-enables. Your controller will output the appropriate control signals for your datapath. Depending on how you design your datapath, you will need different control signals. You may use behavioral Verilog to write the controller, but this is the only module in which you are allowed to do so.

When writing your behavioral Verilog code, you may find it useful to use verilog preprocessor definitions. For instance, you should create symbolic constant definitions for all of the opcodes so that you are not dealing with them numerically. For instance:

`define STOR 17

Then, in your controller you can define your data-memory write enable signal behaviorally like this:

output dmem_wen; wire dmem_wen = (opcode == `STOR);

Writeup and Demo

Your writeup for this lab should include your Verilog code for the datapath and controller only and a matching labeled schematic for the datapath. Also, turn in a simulation output . You will demo your code for the TAs on four programs. One of the programs is in ~amir/cse371/labs/lab4/. The memory output image of this program should be a 4 in the first memory address. If you can get your processor to do this, you are one quarter of the way there. The other programs will be written by the TAs and myself and will test more of the ISA in various combinations. Feel free to write your own short programs or to test your code on the assembly programs you wrote for the first homework assignment. The dmem.out file of your Verilog simulation should resemble the dmem.out file from the functional simulator written in C running the same program.