This will be the shortest lab of the semester. In this lab you will create some of the storage components for your R372 processor. Specifically, you will create the register file and the instruction and data memory modules. For this assigment you will use a combination of both structural and behavioral Verilog.

Exercise 1: 8-entry 16-bit register file (50 points)

Use structural Verilog to design a 8-entry register file component regfile8_16_2r1w with the following interface.

• One 1-bit input clock signal: clk.
• One 1-bit input rst signal: rst.
• Two 3-bit input register read select buses: rsel1 and rsel2.
• One 3-bit input register write select bus: wsel.
• One 1-bit input register write enable signal: wen.
• Two 16-bit output register read data buses: rdata1 and rdata2.
• One 16-bit input register write data bus: wdata.

The register file should have the following behavior:

• Reads are continuous.
• Writes occur on the positive edge of a clock cycle (clk goes from low to high).
• In a given cycle, a write only occurs if the wen signal is high.
• In a given cycle, any two registers may be read and any register may be written.
• On any positive clk edge, if rst is high, then all registers are cleared.

You may design the internals of the register file as you wish but it would probably help if you used hierarchical design and reused some of the components you built in previous assignments, like decoders and muxes.

Create test inputs and a gtkwave timing diagram that show that your register file meets specifications. In the first 8 cycles, write the values 8-15 in registers 0-7, respectively. In the next 6 cycles, read the following register combinations: 0/1, 2/3, 4/5, 6/7, 7/6, and 2/2. Finally, show simultaneous reads and writes in the same cycle. First, write the value 16 into register 0, while simultaneously reading registers 2/3. Then, write the value 17 into register 1, while simultaneously reading registers 0/1. Show your design to the TA so that he/she can ask you some questions about it. Turn in your Verilog code, a labeled schematic for the register file (but not for the muxes, decoders, etc.) and the gtkwave timing diagram.

Exercise 2: 16-bit Memory Blocks (50 points)

Use behavioral Verilog to create instruction and data memory modules with the following interfaces. See this tutorial for help with behavioral verilog. The instruction memory module imem_16 should contain 2¹⁵ 16-bit words and have the following interface:

• One 1-bit input clock signal: clk.
• One 1-bit input reset signal: rst.
• One 16-bit input address bus: addr.
• One 16-bit output bus: rdata.
• One 1-bit output error signal: aerror.

The instruction memory module should implement the following behavioral "task" (see the tutorial for how to implement these).

• load uses the VPI command $readmemh to load the contents of the file "imem.in" into the memory, starting at address 0.

The instruction memory module should have the following behavior:

• Reads should be continuous and there are no writes.
• If the address on bus addr is in the range 0000-7fff, then rdata is memory[addr[14:0]] and aerror is 0.
• If the address on bus iaddr is not in the range 0000-7fff, then rdata is 0 and aerror is 1.
• On a positive clk edge, if rst is high, then the memory executes the load task.

Use the R372 assembler to create an imem.in hex file from the code ~amir/cse371/homeworks/hw1/btree/btree.a. Write a test script that shows your design works by reading the following addresses from instruction memory: 0000, 0001, 0002, 0100, and 8000. Turn in your Verilog code and a simulation output.

Create a 2¹⁵ 16-bit word data memory module dmem_16 with the following interface:

• One 1-bit input clock signal: clk
• One 1-bit input reset signal: rst
• One 16-bit input address bus: addr
• One 1-bit input write enable signal: wen
• One 16-bit output data bus: rdata
• One 16-bit input data bus: wdata
• One 1-bit output signal: aerror

The data memory module implements the following two tasks:

• load uses the VPI command $readmemh to load the contents of the file "dmem.in" into the memory, starting at address 0.
• dump uses the VPI command $writememh to dump the contents of memory into the file "dmem.out".

It also has the following interface:

• Reads are continous.
• Data is written on the rising edge of clk and only if wen is high.
• On a positive clk edge, if wen is high and the address on bus addr is in the range 8000-ffff, then wdata is written into memory[addr[14:0]] and aerror is 0.
• On a positive clk edge, if wen is high and the address on bus addr is not in the range 8000-ffff, then no data is written and aerror is 1.
• If the address on bus addr is in the range 8000-8fff, then rdata is memory[addr[14:0]] and aerror is 0.
• If the address on bus addr is not in the range 8000-8fff, then rdata is 0 and aerror is 1.
• On a positive clk edge, if rst is high, then the memory executes the load task.

Show that your data memory module works by first writing the following data into the corresponding addresses: aaaa into 8000, bbbb into 80ff, cccc into 8100, dddd into 0000, eeee into ff00, and ffff into ffff and then reading the following addresses. Turn in your Verilog code and a simulation output. Show your design to a TA so that he/she can ask you some questions about it.