CSE 371/372
Lab 1

Due:  Friday, February 4 (hand your writeup to a TA).

In this lab you will familiarize yourself with the Icarus Verilog tools through the structural design of some simple combinational circuits. You can view it as trying out your new compiler with the "Hello World!" program. You are to do this assignment completely using structural Verilog, i.e., the only primitives you are allowed to use are the gates: buf, and, or, xor, not, nand, nor, and xnor, wire assignment, and modules which you yourself have defined. Do not use any behavioral primitives. If you need help with structural Verilog, there is a short tutorial here.

Exercise 1: 3-to-8 Decoder (15 points)

A decoder is a combinational circuit that takes an input in binary and translates it into "one-hot" form.  Decoders are very useful in actual computers. The simplest decoder is the 1-to-2 decoder, with singleton input IN and vector output OUT[1:0]. If IN is 0, then OUT[0] is 1 and OUT[1] is 0. If IN is 1, then OUT[1] is 1 and OUT[0] is 0. The more complex decoder is the 2-to-4 decoder with input IN[1:0] and output OUT[3:0]. If IN is 0, then OUT[0] is 1 and all the other OUT[i] are 0.  If IN is 1, then OUT[1] is 1 and all the other outputs are 0.  This form is called "one-hot" because for any input, only one output wire is high. Use structural verilog to design and implement both a 1-to-2 decoder (dec1to2) and a 2-to-4 decoder (dec2to4). Use hierarchical design to put together 1-to-2 and 2-to-4 decoders (and some other gates) to create a 3-to-8 decoder. Do a functional simulation of your decoder to show that all possible 8 cases work correctly. You can do this by implementing your decoder in a file called dec.v and compiling it with the file ~amir/cse371/labs/lab1/dec_test.v in the directory Turn in your verilog code, a labeled, hand-drawn schematic that matches your verilog code, and simulation output. (simulation output is generated by the VPI command \$monitor). See the file ~amir/cse371/labs/lab1/dec_test.v for an example.

Exercise 2: D-Latch, D-Flipflop, and D-Flipflop with Synchronous Reset (15 points)

Use structural verilog to implement a 1-level triggered D-Latch (dlatch_pos) and a positive-edge triggered D-Flipflop (dff_pos). Use hierarchical design.

In real processors, many D-Flipflops also have synchronous reset signals. A synchronous reset signal is an extra input to the D-flipflop (call it R) such that whenever R is high on a positive clock edge, the D-flipflop stores some default value (either 0 or 1). Create two components (dff_pos_srs1 and dff_pos_srs0) which are D-flipflops with synchronous resets that default to 1 and 0 respectively. Again, use hierarchical design here, i.e., you can implement a synchronous reset D-flipflop using a D-flipflop as one of the components. Create your own test file to illustrate the difference between these four components. Turn in your verilog code, matching hand-drawn labeled schematics, and a labeled gtkWave printout (gtkwave readable output, i.e., a dumpfile.vcd file, is generate by the VPI command \$dumpvars. See the file ~amir/cse371/labs/lab1/dec_test.v for an example.

Exercise 3: Ripple-Carry Adder (15 points)

Use structural Verilog to implement a 4-bit ripple-carry adder. Use hierarchical design. Remember, the basic component of the ripple-carry adder is the single-bit full-adder. Show that your adder works for the addition of two positive numbers (with no overflow), two negative numbers (no overflow), a positive number and 0, a negative number and 0, a positive and a negative number that sum to a positive number, a positive and a negative number that sum to a negative number, and a positive and negative number that sum to 0. Turn in your verilog code, a hand-drawn labeled matching schematic, and a simulation output.

Exercise 4: Unsigned Multiplier (15 points)

Use structural verilog to implement a 4-by-4 to 8-bit unsigned multiplier. Use hierarchical design. Hint: you need 3 4-bit adders and some 2-to-1 muxes. Another hint: wire slice selection and concatenation are really useful in this assignment. Turn in your verilog code, a hand-drawn labeled, matching schematic, and a simulation output showing a multiplication where a is 0, one where b is 0, and a few when neither is 0.

Exercise 6: Digital Combination Lock FSM (30 points)

Design a finite state machine (FSM) for a digital combination lock. The lock module has three inputs: clk, grs (global reset), and pushbuttons[3:0]. The lock has one output (open). The output signal open is high when the last sequence of button presses (i.e., high) has been: 3,3,0,1,0. open is low at all other times. The sequence 3,3,3,3,3,0,1,0 is valid.

Your state machine will be clocked. One problem with this is that the button inputs may arrive either out of sync with the clock or last longer than one clock cycle (in real systems, human actions corresponds to thousands if not millions of clock cycles). So when implementing your the lock, it is useful to implement a smaller "helper" FSM first. This FSM (sync_signal) has two inputs (clk and in) and one output out. One copy of this FSM is attached to each input button. The FSM performs two functions. First, it synchronizes the button signal (which may happen at any time relative to the clock) with a falling clock edge. This simulates the fact that the button was pushed some time before the rising edge of the next clock. Second, it restricts the button signal to exactly one clock period. This will allow you to design the lock FSM synchronously (i.e., using the clock as the transition meter), while presenting it with the simplified interface that a high button input in a cycle corresponds to a single button push and that two high signals in consecutive cycles correspond to two independent pushes rather than a single long push.

In addition to this, you can also make the following two simplifying assumptions. First, buttons will not be simultaneously pressed. Second, no button will be pressed for less than one full clock period.

Hint: the easiest way to do this is to create a "one-hot" state machine with one D-flipflop per state. Turn in your verilog code, a tabular description of the FSM, and a functional simulation demonstrating one successful lock sequence, and four different unsucessful lock sequences (including some partially successful ones, e.g., 3,3,0,1,1). Demonstrate your code to a TA. He will combine with our own test vector to see if your lock works in the general case.

Lab Writeup:

Remember that over half of your grade will be determined based on your lab writeups these should be clear, concise and neat-preferably typed. You could have the greatest design in the world but if you cannot convey your idea clearly to the graders and convince them that it works you will not get good marks. Your lab writeups should include a brief explanation of what the circuits are supposed to do and how they do it, clear Verilog code and timing diagrams.