In this final lab, you will take the processor you designed for the previous lab and pipeline it.

Interface

The processor will have the same interface as it did in the previous lab. The notable difference is the values of the instruction and cycle counters. While the cycle counter still increments every cycle, the instruction counter now increments only when an instruction completes.

Structural Specifications and Hints

Again, there are not many structural specifications. You are free to implement the pipeline (and more importantly its control logic) as you wish. The only requirements are:

• Five stages similar to those we discussed in class: fetch, decode and register read, ALU, data cache access, and writeback.
• Full bypassing: MX (both A and B ALU inputs), WX (both A and B ALU inputs), and WM (data memory input).
• Branches are implicitly predicted not-taken.

Assuming you have a working datapath from Lab 4, this lab should actually take you less time than Lab 4 did. Remember, a pipelined datapath and a single-cycle datapath use the same datapath controller. The pipelined datapath simply pipelines the control signals using pipeline registers.

Here is how I would go about doing this lab. First, I would start with a working Lab 4 datapath and controller and add pipeline latches, including latches for the appropriate control signals. This very simple pipeline has no branch, stall, or bypass logic but it should be able to correctly handle instruction sequences that require no stalling or bypassing (i.e., sequences in which dependent instructions are not within 3 instructions of one another) and which have no branches. You can create a little instruction sequence like this to test this basic pipeline.

Next, add support for taken branches. Here you have to recognize a taken branch, and do a flush. Look at the pipelining slides for hints on how to implement flushes. Now, you can add branches to your instruction sequenced to see if this functionality works.

Next, add bypasses. Remember, bypassing is controlled by local logic, so you can add bypasses independently of one another. From homework 3, you should have an idea of how to write an instruction sequence to exercise a particular bypass. Use those.

Finally, add stall logic. Remember, with full bypassing and only single cycle operations (luckily, you do not have to implement multiply in your pipeline), there is only one condition that requires stalling. It should be easy to test for this condition. Look at the pipelining slides for hints on how to implement stalls.

Writeup

Your writeup for this lab should include your schematics and VHDL code, timing diagrams for three test programs, and TA demos for two other programs. The TAs will also ask you questions about your design.

The three test programs are in ~amir/cse371/r372/mbench/. There are three test programs in the sub-directories lab4.prog1, lab4.prog2, and lab4.prog3. They test ALU operations, control instructions, and memory instructions, respectively. You can create LogiBLOX files from the assembly files using the -b assembler option. To make sure that your processor is executing correctly, you can also compare PC and RDVAL traces with traces generated by the simulator using the -t option. The additional -x simulator option prints trace values in hexadecimal form which may be easier to compare. Please use the assembler and simulator in ~amir/cse371/r372/bin.lab/. In addition to these three programs, you can test your processor on programs of your own or use some of the bigger benchmark programs like bubblesort.