In this lab you will use the components you built in the previous lab to create a single cycle implementation for a subset of the R372 instruction set. Your processor should support all instructions except for MULR, SLED, LSWI, LCTR, and CCTR. You will test your processor on four programs, and not all programs use all instructions. Therefore, it is better to have a processor that executes a subset of the instructions correctly than one that executes no instruction correctly.

Interface

The processor you will design will act like a single-program computer with a very simple external interface. You will initialize the processor with a program to execute by loading a specially assembled file into the LogiBLOX instruction memory.

Even though you need not support LCTR and CCTR, your processor should still internally implement the instruction and cycle counter registers. Both counters should initially be set to 0. The instruction counter should increment when an instruction finishes execution. The cycle counter should increment when on every cycle. Both counters should stop incrementing once the HALT instruction has been executed. Since this is a single-cycle design, both counters should effectively increment in lockstep. The values in these registers (which you need not implement as part of the register file) will help to determine whether or not your processor executes correctly. Your processor will have the following interface:

• 1-bit input signal CLK
• 1-bit input signal RESET. When RESET is asserted, the processor resets the program counter and the instruction and cycle counter registers to 0. It begins executing as soon as the RESET signal is de-asserted.
• 16-bit output signal ICNT. This is the value of the instruction counter register.
• 16-bit output signal CCNT. This is the value of the cycle counter register.
• 16-bit output signal PC. This is the value of the current program counter.
• 16-bit output signal RDVAL. This is the value on the register file write port.

Structural Specifications and Hints

There are not a lot of structural specifications for this lab, you are free to design the processor as you wish. You may use either schematics or VHDL or both. You will probably find it easiest to implement the datapath schematically, and the controller using VHDL. If you look carefully at the ISA, you will also see that parts of it have been designed so that certain bits in some instructions can be used as explicit control signals. This is true for branches, the ALU, and the shifter. If you exploit this fact (which you don't have to) your controllers may be simpler.

Writeup

Your writeup for this lab should include your schematics and VHDL code, timing diagrams for three test programs, and TA demos for two other programs. The TAs will also ask you questions about your design.

The three test programs are in ~amir/cse371/r372/mbench/. There are three test programs in the sub-directories lab4.prog1, lab4.prog2, and lab4.prog3. They test ALU operations, control instructions, and memory instructions, respectively. You can create LogiBLOX files from the assembly files using the -b assembler option. To make sure that your processor is executing correctly, you can also compare PC and RDVAL traces with traces generated by the simulator using the -t option. The additional -x simulator option prints trace values in hexadecimal form which may be easier to compare. Please use the assembler and simulator in ~amir/cse371/r372/bin.lab/. In addition to these three programs, you can test your processor on programs of your own or use some of the bigger benchmark programs like bubblesort.