In this lab you will create some of the storage components for your R372 processor. Specifically, you will create the register file and the instruction and data memory modules. For this assigment you will use both schematics and VHDL.

Exercise 1: 8-entry 16-bit register file (50 points)

Use schematics to design an 8-entry 16-bit register file to the following specifications. First, here are the interface signals and buses:

• Two 16-bit output register read data buses: RDATA1 and RDATA2.
• One 16-bit input register write data bus: WDATA.
• Two 3-bit input register read select buses: RSEL1 and RSEL2.
• One 3-bit input register write select bus: WSEL.
• One 1-bit input register write enable signal: WEN.
• One 1-bit input clock signal: CLK.

The register file should have the following behavior:

• Writes occur on the positive edge of a clock cycle (CLK goes from low to high).
• Reads occur in the second half of the cycle (CLK low). During the first half of the the cycle (CLK high), the read data buses RDATA1 and RDATA2 are in Z ("high-impedance") mode.
• In a given cycle, a write only occurs if the WEN signal is high.
• In a given cycle, any two registers may be read and any register may be written.
• If the same register is both read and written in the same cycle, then the value read should be equal to the value written.

You may design the internals of the register file as you wish but it would probably help if you used hierarchical design and reused some of the components you built in previous assignments, like decoders, muxes, and tri-state buffers.

Create test inputs and a timing diagram that show that your register file meets specifications. In the first 8 cycles, write the values 8-15 in registers 0-7, respectively. In the next 6 cycles, read the following register combinations: 0/1, 2/3, 4/5, 6/7, 7/6, and 2/2. Finally, show simultaneous reads and writes in the same cycle. First, write the value 16 into register 0, while simultaneously reading registers 2/3. Then, write the value 17 into register 1, while simultaneously reading registers 0/1. Show your design to the TA so that he/she can ask you some questions about it. Turn in your schematics and timing diagram.

Exercise 2: 16-bit Memory Blocks (50 points)

Xilinx provides two tools for creating and initializing small random access memories (RAMs): Core Generator and LogiBLOX. Look through the help files to learn how to use these tools. For this exercise, you will create RAM macros using either CoreGenerator or LogiBLOX and around them build schematics that behave like memories we can use in an R372 processor.

One of the problems with both CoreGenerator and LogiBLOX is that they can only build memories that have 256 (2^8) words. R372 is a 16-bit instruction set which means it can address 64K (2^16) words. The lower 32K (2^15) words are instruction memory, the upper are data memory. Does this mean that the memory implementations you will create will have 128 RAM macros each? No.

Your instruction memory will have a single RAM macro that houses the first 256 instruction words (addresses 0000-00ff). Access to any of the "missing" 127 RAMs will result in an error. This means that your instruction memory will only support programs with fewer than 256 static instructions. So what.

Similarly, your data memory will use two RAM macros. One will house the first 256 data words (addresses 8000-80ff). The other will house the last 256 data words (addresses ff00-ffff). Access to any of the "missing" 126 RAMs will result in an error. This means that your data memory will only support programs that use fewer than 256 heap words and fewer than 256 stack words. Again, so what.

Use one 256-by-16 synchronous RAM primitive and additional schematics to design an instruction memory macro with the following interface:

• One 16-bit output bus: IRDATA
• One 16-bit input bus: IADDR
• One 1-bit output signal: IAERROR

The instruction memory macro should have the following behavior:

• If the address on bus IADDR is in the range 0000-00ff, then IRDATA is IRAM[IADDR[7:0]] and IAERROR is 0.
• If the address on bus IADDR is not in the range 0000-00ff, then IDATA is in the Z state and IAERROR is 1.

Initialize the RAM using the memory file :eniac:~amir/cse371/r372/mbench/queens/queens.insn.mem. Show that your designs work by reading the following addresses from instruction memory: 0000, 0001, 0002, 0100, and 8000. Turn in your schematics and timing diagrams.

Use two 256-by-16 synchronous RAM primitives and additional schematics to design a data memory macro with the following interface:

• One 16-bit output data bus: DRDATA
• One 16-bit input data bus: DWDATA
• One 16-bit input bus: DADDR
• One 1-bit input signal: CLK
• One 1-bit input signal: WEN
• One 1-bit output signal: DAERROR

The data memory macro should have the following behavior:

• Data is written on the rising edge of the clock (CLK goes low to high) and only if WEN is high.
• If WEN is high DRDATA is in the Z state.
• On a positive CLK edge, if WEN is high and the address on bus DADDR is in the range 8000-80ff, then DWDATA is written into DRAM0[DADDR[7:0]] and DAERROR is 0.
• On a positive CLK edge, if WEN is high and the address on bus DADDR is in the range ff00-ffff, then DWDATA is written into DRAM1[DADDR[7:0]] and DAERROR is 0.
• On a positive CLK edge, if WEN is high and the address on bus DADDR is in neither range, then DWDATA is not written into DRAM1[DADDR[7:0]] and DAERROR is 1.
• If WEN is low and the address on bus DADDR is in the range 8000-80ff, then DRDATA is DRAM0[DADDR[7:0]] and DAERROR is 0.
• If WEN is low and the address on bus DADDR is in the range ff00-ffff, then DRDATA is DRAM1[DADDR[7:0]] and DAERROR is 0.
• If WEN is low and the address on bus DADDR is in neither range, then DRDATA is in the Z state and DAERROR is 1.

Leave DRAM0 and DRAM1 uninitialized. Show that your design works by first writing the following data into the corresponding addresses: aaaa into 8000, bbbb into 80ff, cccc into 8100, dddd into 0000, eeee into ff00, and ffff into ffff and then reading the following addresses. Turn in your schematics and timing diagrams.

Design a finite state machine that will copy the lower 256 words of instruction memory to the lower 256 words of data memory. The simplest way to do this is probably using registers a couple of registers and a couple of incrementers. Show your design to a TA so that he/she can ask you some questions about it. Turn in your schematics.