Due: Friday, February 6 at the close of Lab (just hand your writeup to a TA).
In this lab you will familiarize yourself with the Xilinx Foundation Series CAD tool through the design of simple combinational circuits. You can view it as trying out your new compiler with the "Hello World!" program. You will also learn different approaches to designing and implementing digital circuits in Xilinx. Prior to starting the lab, read Getting Started with the XILINX M1 Foundation F2.1i Tools. Expect this lab to take a long time, so get started early.
Exercise 0A: Working with Schematics (0 points)
This exercise will not be graded, but you should do it anyway to familiarize yourself with the system. This exercise will also allow you to create some directories and files which you will need in your other projects.
The tutorial will walk you through this exercise. Follow the steps described in schematic entry section of the tutorial to create the specified circuit. Do the functional simulation of the design as described in simulation section. Show all three input signals and the output in the simulation diagram. Implement and download the design into the device on the demo board as described in the implementation and configuration sections of the tutorial.
1. First create a folder users\your_name on the C: drive in which you will save your projects. Give it your last name, but limit it to 8 characters. Xilinx will cause problems later on whenever you use names of folders and files which have more than 8 characters. When you create a project in Xilinx, the program creates a new folder with the same name as the project as well as a PDF (project description) file, which it uses to recognize projects. Both of these items should be placed in your folder.
2. Start with the tutorial Creating a new Project: Schematic Entry on the Tutorial web pages.
4. Next, you will do a functional simulation in order to check that the logic circuit gives you the required function. Follow the tutorial on Functional Simulation . Make sure that the "Functional" appears in the pull down menu at the bottom of the simulator window. Check that your circuit works, if the circuit does not work properly, check your schematic and correct it. Read also the section on Common Mistakes. When you modify your schematic you should update the simulator. When the schematic has been modified save it and go to the OPTIONS menu -> EXPORT NETLIST and UPDATE SIMULATION in order to ensure that the simulator will use the latest schematic.
5. If the circuit works as expected:
Exercise 0B: Working with VHDL (0 points)
Another approach in logic design is to use the hardware description language (HDL). It is a special language used to describe what your hardware should do. You will now design the same circuit using the VHDL hardware description language. Follow the steps described in the VHDL design entry section of the tutorial. Repeat the functional simulation and download the design.
Exercise 1A: Schematic Implementation of 3-to-8 Decoder (20 points)
A decoder is a combinational circuit that takes an input in binary and translates it into "one-hot" form. Decoders are very useful in actual computers. The simplest decoder is the 1-to-2 decoder, with singleton input IN0 and outputs OUT0 and OUT1. If IN0 is 0, then OUT0 is 1 and OUT1 is 0. If IN0 is 1, then OUT1 is 1 and OUT0 is 0. The more complex decoder is the 2-to-4 decoder with inputs IN0 and IN1 and outputs OUT0, OUT1, OUT2, and OUT3. In bus form, the inputs can be written as IN[1:0] and the outputs as OUT[3:0]. If IN[1:0] is 0, then OUT[0] is 1 and all the other OUT[i] are 0. If IN[1:0] is 1, then OUT[1] is 1 and all the other outputs are 0. This form is called "one-hot" because for any input, only one output wire is high.
Use schematics to design and implement both a 1-to-2 decoder and a 2-to-4 decoder. Create a symbol for each of these decoders. Use hierarchical design to put together 1-to-2 and 2-to-4 decoders (in some combination) to create a 3-to-8 decoder. Create a symbol for this decoder as well. Connect your 3-to-8 decoder symbol to input and output pads. Do a functional simulation of your decoder to show that all possible 8 cases work correctly. Turn in your schematics and simulation output.
Connect the 3-to-8 decoder symbols to input and output pads corresponding to the switches and LEDs on the Xilinx board, respectively.
Exercise 1B: VHDL Implementation of 3-to-8 Decoder (20 points)
Repeat Exercise 1A, but this time implement the decoders using VHDL. You must use hierarchical design here as well. Do a similar functional simulation. Turn in your VHDL code and simulation output.
Exercise 2: VHDL Implementation of a 7-Segment Decimal Display Decoder (30 points)
The 7-segment displays on the Digilab board are shown in the figure
below. Each display consists of seven LEDs labeled `a' through `g'. The
input to your circuit is a four bit word and the outputs are seven signals
that drive the 7-segment LED display. For example, if the binary value
of the input is 0, all segments except `g' should be illuminated. If the
binary value of the input is 1, segments `b' and `c' should be illuminated
and so on. If the binary value is greater than 10, then you would
need two displays. Two notes about the LED displays. First, a segment
is illuminated when its input is low. Second, there are four displays and
you need to drive the anode signal high of the ones you are using.
Figure 4: Seven-segment displays on the Digilab board: (a) Seven-segment display; (b) four displays with common anode; (c) LED connections
Use VHDL to specify the desired behavior of your circuit. The with-select-when construct would be particularly appropriate for this task; refer to the end of Section 9c of the VHDL tutorial for an example of how this construct is used in practice. Functionally simulate your design. Compile your design and download it into the device on the Digilab board. Refer to the section on seven segment displays in the Digilab tutorial to find out which pins drive which display elements. Assign pins properly in your design. Use four of the slide switches as input and show that your design works by trying out all possible binary combinations. Turn in the VHDL code for your design timing diagrams from the simulation, and demonstrate your circuit to the TA.
Exercise 3: Implementation of Digital Combination Lock FSM (30 points)
Design a finite state machine (FSM) for a digital combination lock. The inputs to the lock are four push button switches. The output is one of the LEDs which lights up when a user presses the four buttons in the following sequence: 4, 2, 1, 3. You may use the other LEDs to help you debug your FSM. Use the onboard oscillator as your clock source. Remember that a button may be pushed for several cycles. You may use either schematics or VHDL for this exercise. Turn in your schematics/VHDL, a functional simulation demonstrating one successful lock sequence, and four different unsucessful lock sequences, and demonstrate your circuit to the TA.
HINT: when implementing your digital combination lock, it is useful to implement a smaller "helper" FSM first. This FSM has one input and one output. One copy of this FSM is attached to each input button. The FSM performs two functions. First, it synchronizes the button signal (which may happen at any time relative to the clock) with a falling clock edge. This simulates the fact that the button was pushed some time before the rising edge of the next clock. Second, it restricts the button signal to exactly one clock period. The speed with which a human can push and release a button is on the order of tens or hundreds of milliseconds, which is the equivalent of many thousands of clock cycles. Restricting the output to only a single cycle, allows us to design the lock FSM synchronously (i.e., using the clock as the transition meter), while presenting it with the simplified interface that a high button input in a cycle corresponds to a single button push and that two high signals in consecutive cycles correspond to two independent pushes rather than a single long push. Of course, with your "helper" FSM, the case of button pushes in consecutive clock cycles should be impossible (a human would not be able to push a button twice that fast).
Lab Writeup:
Remember that over half of your grade will be determined based on your lab writeups these should be clear, concise and neat-preferably typed. You could have the greatest design in the world but if you cannot convey your idea clearly to the graders and convince them that it works you will not get good marks. Your lab writeups should include a brief explanation of what the circuits are supposed to do and how they do it, clear schematics or VHDL listings and timing diagrams.