Datapath and Control

1. (5 points) The datapath we went over in class supports arithmetic, arithmetic immeidate, load, store, conditional branch, and unconditional jump instructions. For this exercise, you will modify the datapath to support the MIPS instruction jal (jump and link). You can look up the semantics of this instruction in Appendix A in the book. Describe the necessary changes. Show and label any new structures, buses, muxes, and control signals, or any changes to current muxes, or control signals. You may either print this datapath and add the changes to it, or draw your own.

2. (5 points) Repeat exercise 1 for the jr instruction.

3. (10 points) Modify the multi-cycle FSM (slides #57 and #58) to implement the two new instructions.

4. (10 points) Using a paragraph and a diagram, explain how you would construct a datapath for a register-memory architecture: this is an architecture whose arithmetic operations have one register operand and one memory operand. Answer the question assuming "register indirect" addressing (i.e., addresses are specified as register contents plus immediate). What optimization could you perform on the datapath if the ISA supported a less general form of addressing, "displacement" addressing (i.e., addresses are specified as register contents)?

Pipelining

5. (5 points) P+H exercise 6.28

6. (5 points) P+H exercise 6.29

7. (10 points) P+H exercise 6.30 (Note: this exercise is about loop unrolling, a technique we did not cover in class. Read the book to learn about it.)

8. (10 points) For the code sequence from problem 7 (the one showed in the book), draw three pipeline diagrams: one showing execution with no bypassing, one showing only MX bypassing (to both ALU inputs), and one showing full bypassing.

R372 Simulator Programming

9. (40 points) For this assignment, you will be required to modify the R372 simulator, rather than write an assembly language program for it. You will modify the file simulator.c to simulate the delays of a 5-stage MIPS-style pipeline with different bypassing configurations. The simulator has two counter registers: counters[0] is the instruction counter, and counters[1] is the cycle counter. Your job is to modify the code such that the cycle counter reflects the actual number of cycles the program would take to execute on a pipeline with a given configuration.

The easiest way to do this is probably to compute the number of stall cycles each instruction experiences. Since this is a simple "in-order" pipeline, individual instruction stalls add. So, as each instruction is simulated, counters[1] is incremented by 1 plus any number of stall cycles. You can compute the stall cycles by checking the registers the current instruction reads against the registers the previous instructions write. Look for the variables ri1, ri2, ro, ro_1, and ro_2 for clues.

The simulator has a slightly new interface which you can learn about by simply running it with no arguments. Basically, the filename is now the first argument and all other arguments are optional. The old argument -[b|x] has been replaced with an optional argument [-b] (the default is hexadecimal interface). The old argument -[s|t] has been replaced with an optional argument [-t] (the default is silent execution). The three new optional arguments are -[mx], -[wx], and -[wm] which specify MX, WX, and WM bypassing, respectively. The default is no bypassing.

Make a copy of the directory~amir/cse371/r372/src/ to your local directory and make the modifications there. You may test your modifications on the multiply-divide assembly programs you wrote, but the only thing you must turn in for this assignment is an electronic copy of your modified simulator.c.