CSE 371: Spring 2004

CSE 371/372: Digital Systems Organization and Design
Spring 2004
CLASS SCHEDULE

Instructor: Amir Roth (amir@cis)
603 Levine
Office hours: TR 10-11 (or by appointment)

TA: Bill Kandylas (kandylas@seas)
Office hours: MW 12-1:30 GRW 076

TA: Gunjan Gupta (ggupta@seas)
Office hours: TR 4-5:30 GRW 076

Meeting Times and Places

Lecture: Hielmeier Hall, TR 12-1:30
Recitation: NONE

Course Description

This is the first time I am teaching this class, and I will teach it (espeically the 371 part) somewhat differently than it was taught in the past. We will cover the following topics:

performance and cost
instruction set design
basic transistors and digital circuits
computer arithmetic
datapath and control
pipelining
memory hierarchy
I/O

Here is the CLASS SCHEDULE.

Reading Materials and Resources

We will use one textbook:

Patterson and Hennessy, "Computer Organization and Design: The Hardware Software Interface" (THIRD edition).

I will supply you with any additional reading material. Also, class notes will be available on-line. Check the ever-changing CLASS SCHEDULE for notes. Hard copy versions will be available at the beginning of each class, extra copies will be placed in bins outside of Levine 502.

Homeworks

There will be 6 homework assignments, each consisting of problems to be worked out by hand. Homework is due at the beginning of the class period for which it is assigned. Late homework is not accepted unless prior arrangements are made. You may ask myself, the TAs, or each other for assistance, but please cite your references on the assignment. Check the CLASS SCHEDULE for homeworks.

Exams

There will be a midterm and a final. The final will be during its slotted time. The mid-term will be in class and is tentatively scheduled for March 2.

Labs

In addition to the homeworks, which will largely be "pencil-and-paper" exercises, there will also be 6 lab exercises in which you will incrementally impelement a pipelined processor for a simple RISC ISA. These labls will comprise the 372 part of the course. Like homeworks, labs will be assigned via the CLASS SCHEDULE. For help with the labs, you might want to consult the EE201 (the EE department's equivalent of 371) VHDL Tutorial and/or Xilinx Foundation Tutorial.

Grading

Grading breakdown for 371 is as follows:

Homeworks: 30% (6 homeworks, 5% each)
Mid-term exam: 30%
Final exam: 40%

Grading breakdown for 372 is as follows:

Labs 1-3 (done individually): 30% (10% each)
Labs 4-5 (done in groups of two): 40% (20% each)
Lab 6 (done in groups of two): 30%

If you want to cheat, go ahead. Getting caught will result in (at best) a non-negotiable SUBTRACTION of the corresponding maximum from your overall grade. Translation, it's better to skip an assignment than copy someone else's and get caught.