| Class# / Date | Topic | Slides | Readings | Homework |
| 1. 9/7 (R) | Introduction | |||
| 2. 9/12 (T) | Technology Cost Performance |
H&P: Chapter 1
Moore, "Cramming More Components onto Integrated Circuits" | ||
| 3. 9/14 (R) | Instruction Sets | H&P: Chapter 2, Appendix C (RISC architectures) and
D (X86) (for reference)
Cocke, "The Evolution of RISC Technology at IBM" | ||
| 4. 9/19 (T) | ||||
| 5. 9/21 (R) | Datapaths Pipelining |
H&P: Appendix A | ||
| 6. 9/26 (T) | Homework 1, Solutions | |||
| 7. 9/28 (R) | Memory Hierarchy I | H&P: Chapter 5.1-5.5 Jouppi, "Improving Direct-Mapped Cache Performance..." |
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| 8. 10/3 (T) | ||||
| 9. 10/5 (R) | Memory Hierachy II | H&P: Chapter 5.8-5.9 | ||
| 10. 10/10 (T) | Multiple Issue Static Scheduling |
H&P: Chapter 4 Edmondson et al., "Superscalar Instruction Execution on the Alpha 21164 Microprocessor" |
Homework 2, Solutions | |
| 11. 10/12 (R) | ||||
| 12. 10/17 (T) | ||||
| 11. 10/19 (R) | Dynamic Scheduling | Kessler, "The Alpha 21264 Microprocessor" | ||
| 14. 10/26 (R) | Project Description and Review | |||
| 15. 10/31 (T) | Midterm | F06 (this years) midterm and solutions F04 midterm and solutions F03 midterm and solutions |
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| 16. 11/2 (R) | Dynamic Scheduling | |||
| 17. 11/7 (T) | ||||
| 18. 11/9 (R) | Data-Level Parallelism |
H&P: Appendix G | Homework 3, Solutions | |
| 19. 11/14 (T) | ||||
| 20. 11/16 (R) | Thread-Level Parallelism |
H&P: Chapter 6 Eggers et al., "Simultaneous Multithreading: A Platform for Next Generation Processors" |
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| 21. 11/21 (T) | ||||
| 22. 11/28 (T) | ||||
| 23. 11/30 (R) | Virtualization and the OS | H&P: Chapter 5.10-5.11, 7.1-7.3, 7.10 | Homework 4, Solutions | |
| 24. 12/5 (T) | ||||
| 25. 12/7 (R) | Buffer | |||
| 26. 12/15 (F) | Final (9-11) | F04 final and solutions F03 final and solutions |