Andrew D. Hilton

I finished my PhD at the University of Pennsylvania in summer of 2010, where I used to be a student in the Architecture and Compilers Group. While I was there, I was advised by Amir Roth. I currently work at IBM in Research Triangle Park, North Carolina as part of the performance modelling and analysis team. I also teach at Duke as an adjunct professor in the computer science department. Here is my cv. This page mostly has information about my activities in graduate school: my dissertation research, and the courses that I taught at UPenn.

My primary research interest in graduate school was in energy-efficient load latency tolerance. Loads which miss the data cache degrade performance in any type of core: in-order or out-of-order. When a cache miss occurs, the processor may be able to execute some independent instructions, but if the miss is sufficiently long, the processors critical execution resources fill up (the issue queue and physical registers in out-of-order, the pipeline latches in in-order), and the pipeline stalls. The miss need not go all the way to memory: in an in-order pipeline, even L2 hits stall the processor, and in an out-of-order pipeline L3 hits can cause stalls.

Load latency tolerance (LLT) addresses these scenarios. In LLT, cache misses and their dependent instructions are deferred, i.e., shunted aside, releasing their execution resources, allowing younger miss-independent instructions to execute. When the miss returns, the loads and their dependents are re-injected into the core, re-acquire resources and execute. LLT is compelling but initial designs were impractical and inefficient, requiring several new, bespoke structures and deferring and re-executing too many instructions to justify their performance gains.

My dissertation focused on re-formulating LLT in the context of existing micro-architectures, re-purposing existing structures while adding minimal complexity and overhead. I developed BOLT (Better Out-of-order Latency Tolerance) and iCFP (In-order Continual Flow Pipeline), out-of-order and in-order LLT designs that are complexity and energy efficient. BOLT and iCFP implement the re-execution of miss-dependent instructions as an alternative use of multi-threading hardware, maximizing re-use of existing structures. They avoid associative structures for load and store management, favoring simple, low-overhead indexed structures. Additionally, they employ simple pruning techniques to minimize re-execution overheads.

Dissertation:

Publications:

Teaching:

I was selected by the Center for Teaching and Learning as one of six recipients of their Graduate Fellowship for Teaching Excellence for 2008-09.

I taught the following classes:
I TAed the following classes:

Other:

My WPE-II exam was on Hardware for Exploiting Data Level Parallelism in Spring 2006.
This exam involves reading 3-4 papers on a topic, providing a written analysis, and giving a roughly 45 minute talk.

Before coming to Penn, I was an undergraduate and then Masters student at Georgia Tech. My advisor there was Olin Shivers.

Contact Info:

Department of CIS
Levine Hall
3330 Walnut Street
Philadelphia, PA 19104-6389

Email: a d h i l t o n @ c i s . u p e n n. e d u