With processor speed doubling every 18 months, more and more system functionalities are implemented as software (SW) in the design process of embedded systems. Selecting the ``right'' RTOS before the SW is developed is very important since the SW-implemented functionalities usually have timing properties to satisfy, and designers need to be confident that the RTOS can maintain these timing properties. In this paper, we present an RTOS modeling tool based on SystemC to help designers gain confidence in their RTOS selection. With our tool, RTOS models can be readily implemented by employing the SystemC thread primitives (SC\_THREAD) and simulation engine. Any other components integrable with SystemC can be integrated in our simulation environment.
Our tool is configurable to support modeling and timed simulation of most popular embedded RTOSs. Timing fidelity is achieved by using delay annotation. To model a specific RTOS, a user only needs to (1) set a few parameters to configure the RTOS state machine, (2) provide OS related timing information, and (3) ``plug in'' required driver module(s). The OS timing information can be derived from benchmark data provided by the IC companies and OS vendors. Since OS code directly interfaces with HW and typically executes in on-chip memory, the benchmark results can be trusted in general.
A number of technical challenges must be overcome before we can build our tool. One important problem is how to reduce the synchronization overhead in the simulation. Most previous research work on time stamp prediction of future events is based on an unrealistic assumption that a SW process executes on its dedicated HW processor. We devise an algorithm to predict the time stamp of the next OS-wide event based on the more realistic assumption that multiple processes execute concurrently on a processor, managed by a priority driven scheduler.
Another problem associated with the delay annotation timing model is that the coarse granularity of the clock step may make the clock advance over the time stamp at which an input event is supposed to be handled. In general, this problem hurts the timing fidelity, i.e., the actual interrupt response latency caused by the OS being modeled cannot be measured. We solved this problem by automatically splitting the clock advance step when necessary.
Experiments show that the accuracy of our modeling approach is quite acceptable. By avoiding using an instruction set simulator, our tool can speed up the simulation by more than 3 orders of magnitude.