This talk will first describe why the design of reliable systems will be a key grand challenge for computer architects for the next decade. As technology scales further, hardware will face numerous sources of errors, including aging or wear-out, process variations, high-energy particle strikes, insufficient burn-in, and design bugs. Designing systems that operate reliably in spite of the underlying unreliable hardware will be key to meeting the promise of Moore's law over the next several years.

The RAMP project (Reliability Aware MicroProcessors) has developed several new architecture level tools and techniques for understanding and improving hardware reliability, and has begun a recent collaborative effort to develop a software-driven unified framework for both hardware and software reliability. This talk will focus on our efforts to address the problem of aging or lifetime reliability.

Smaller device dimensions and increasing power densities are threatening processor lifetimes due to wear-out mechanisms such as gate-oxide breakdown and electromigration. We observe that current methodologies for qualifying lifetime reliability are overly conservative since they assume worst-case operating conditions, thereby unnecessarily constraining performance and/or increasing cost. We make the case that lifetime reliability awareness at the architecture level can mitigate this problem by designing processors that leverage actual workload behavior for reliability benefit. I will present new tools and techniques to achieve this goal, including the RAMP architecture-level lifetime reliability evaluation methodology and the dynamic reliability management technique to improve processor lifetime.

This talk is largely based on joint work with Jayanth Srinivasan (UIUC), Pradip Bose (IBM), and Jude Rivers (IBM).

Bio:
Sarita V. Adve is Professor in the Department of Computer Science at the University of Illinois at Urbana-Champaign.  Her research interests are in computer architecture and systems, with a current focus on power-efficient and reliable systems. She was named a UIUC University Scholar in 2004 and received an Alfred P. Sloan Research Fellowship in 1998, IBM Faculty/Partnership Awards in 2005, 1998, and 1997, and a National Science Foundation CAREER award in 1995. She served on the National Science Foundation's CISE directorate's advisory committee from 2003 to 2005 and on the expert group to revise the Java memory model from 2001 to 2005. She received the Ph.D. degree in Computer Science from the University of Wisconsin - Madison in 1993.  Before joining Illinois, she was on the faculty at Rice University from 1993 to 1999.

Tuesday, September 19, 2006

3:00 pm - 4:15 pm

Wu & Chen Auditorium

101 Levine Hall