|
Decoupled Store Completion/Silent Deterministic Replay: Enabling Scalable
Data Memory for CPR/CFP Processors.
(pdf)
Andrew Hilton and Amir Roth
ISCA, June 2009.
INVISIFENCE: Performance-Transparent Memory Ordering in Conventional Multiprocessors.
(pdf)
Colin Blundell, Milo M. K. Martin and Thomas F. Wenisch
ISCA, June 2009.
SoftBound: Highly Compatible and Complete Spatial Memory Safety for C.
(pdf)
Santosh Nagarakatte, Jianzhou Zhao, Milo M. K. Martin and Steve Zdancewic
PLDI, June 2009.
iCFP: Tolerating All Level Cache Misses in In-Order Processors.
(pdf)
Andrew Hilton, Santosh Nagarakatte, and Amir Roth
HPCA, February 2009.
Token Tenure: PATCHing Token Counting Using Directory-Based Cache Coherence.
(pdf)
Arun Raghavan, Colin Blundell, and Milo M. K. Martin
MICRO, November 2008.
HardBound: Architectural Support for Spatial Safety of the C Programming Language.
(pdf)
Joe Devietti, Colin Blundell, Milo M. K. Martin, and Steve Zdancewic
ASPLOS, March 2008.
Making the Fast Case Common and the Uncommon Case Simple in Unbounded
Transactional Memory.
(pdf)
Colin Blundell, Joe Devietti, E Christopher Lewis, and Milo M. K. Martin
ISCA-34, June 2007.
Ginger: Control Independence Using Tag Rewriting.
(pdf)
Andrew Hilton and Amir Roth
ISCA-34, June 2007.
Serialization-Aware Mini-Graphs: Performance with Fewer Resources.
(pdf)
Anne Bracy and Amir Roth
MICRO-39, December 2006.
NoSQ: Store-Load Communication without a Store Queue.
(pdf)
Tingting Sha, Milo M.K. Martin, and Amir Roth
MICRO-39, December 2006.
Subleties of Transactional Memory Atomicity Semantics.
(pdf)
Colin Blundell, E Christopher Lewis, and Milo M. K. Martin
Computer Architecture Letters, Volume 5, Number 2, November 2006.
Store Vulnerability Window (SVW): A Filter and Potential Replacement for
Load Re-Execution.
(pdf)
Amir Roth
JILP, Vol. 8, September 2006.
This page last modified Friday, 12-Jun-2009 20:36:01 EDT
|