Penn ACG
ACG Home + Pubs by Year + Pubs by Topic + Reading Group + WICArch +
Faculty
Milo Martin
Joe Devietti (joining in 2013)
Affiliated Faculty
Rajeev Alur
Steve Zdancewic
Students
Christian Delozier
Laurel Emurian
Sela Mador-Haim
Arun Raghavan
Abhishek Udupa
Alumni & Past Members
Santosh Nagarakatte, PhD
Tingting Sha, PhD
Colin Blundell, PhD
Drew Hilton, PhD
Anne Bracy, PhD
Vlad Petric, PhD
Marc Corliss, PhD
James Anderson, MSE
Vivek Rane, MSE
Neeraj Eswaran, MSE
Margaret DeLap, MSE
Matt Jacobs, MSE
Prashant Prahlad, MSE
Joe Devietti, BSE
Prof. Amir Roth
Prof. E Christopher Lewis
Projects
SoftBound
DISE
Mini-graphs
Pre-execution
RENO
ON-Core
Papers & Talks
by year
by topic
Pictures







Facilities
We do the bulk of our work on 128-processor Linux cluster managed by the Liniac Project.
Links
WWW Architecture
Microprocessor Report
Credits
(c) maystar designs
modified by anne bracy
Welcome!

The Penn CIS Architecture and Compilers Group (ACG) explores a wide range of topics in architectures, compilers, and their intersection. Our work is motivated by the dramatic changes in the way we use machines and the constraints that are imposed on their design. See our projects.

If you are a current or prospective grad student and are interested in our group, please do not hesitate to contact any of us (faculty or students). There are lots of interesting projects going on, and there are many ways to get involved. You may also want to check out the reading group.


Recent Papers and Talks

Multicore Acceleration of Priority-based Schedulers for Concurrency Bug Detection(pdf)
Santosh Nagarakatte, Sebastian Burckhardt, Milo M K Martin and Madan Musuvathi
PLDI, June 2012.

Watchdog: Hardware for Safe and Secure Manual Memory Management and Full Memory Safety(pdf)
Santosh Nagarakatte, Milo M K Martin and Steve Zdancewic
ISCA, June 2012.

Computational Sprinting(pdf)
Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch and Milo M. K. Martin
HPCA, February 2012.

Formalizing LLVM Intermediate Representation for Verified Program Transformations(pdf)
Jianzhou Zhao, Santosh Nagarakatte, Milo M K Martin and Steve Zdancewic
POPL, January 2012.

RetCon: Transactional Repair without Replay(pdf)
Colin Blundell, Arun Raghavan, and Milo M K Martin
ISCA, June 2010.

CETS: Compiler Enforced Temporal Safety for C (pdf)
Santosh Nagarakatte, Jianzhou Zhao, Milo M K Martin and Steve Zdancewic
ISMM, June 2010.

Overcoming an Untrusted Computing Base: Detecting and Removing Malicious Hardware Automatically (pdf)
Matthew Hicks, Murph Finnicum, Samuel T King, Milo M K Martin and Jonathan M Smith
31st IEEE Symposium on Security and Privacy, May 2010.

SMT-Directory: Efficient Load-Load Ordering for SMT(pdf)
Andrew Hilton and Amir Roth
IEEE Computer Architecture Letters, Vol 12, May 2010.

BOLT: Energy-Efficient Out-of-Order Latency-Tolerant Execution (pdf)
Andrew Hilton and Amir Roth
HPCA, Feb 2010.

iCFP: Tolerating All Level Cache Misses in In-Order Processors (pdf)
Andrew Hilton, Santosh Nagarakatte, and Amir Roth
IEEE MICRO, Vol 30, No. 1, Jan./Feb., 2010.

Decoupled Store Completion/Silent Deterministic Replay: Enabling Scalable Data Memory for CPR/CFP Processors. (pdf)
Andrew Hilton and Amir Roth
ISCA, June 2009.

INVISIFENCE: Performance-Transparent Memory Ordering in Conventional Multiprocessors. (pdf)
Colin Blundell, Milo M. K. Martin and Thomas F. Wenisch
ISCA, June 2009.

SoftBound: Highly Compatible and Complete Spatial Memory Safety for C. (pdf)
Santosh Nagarakatte, Jianzhou Zhao, Milo M. K. Martin and Steve Zdancewic
PLDI, June 2009.

iCFP: Tolerating All Level Cache Misses in In-Order Processors. (pdf)
Andrew Hilton, Santosh Nagarakatte, and Amir Roth
HPCA, February 2009.

Token Tenure: PATCHing Token Counting Using Directory-Based Cache Coherence. (pdf)
Arun Raghavan, Colin Blundell, and Milo M. K. Martin
MICRO, November 2008.

HardBound: Architectural Support for Spatial Safety of the C Programming Language. (pdf)
Joe Devietti, Colin Blundell, Milo M. K. Martin, and Steve Zdancewic
ASPLOS, March 2008.

Making the Fast Case Common and the Uncommon Case Simple in Unbounded Transactional Memory. (pdf)
Colin Blundell, Joe Devietti, E Christopher Lewis, and Milo M. K. Martin
ISCA-34, June 2007.

Ginger: Control Independence Using Tag Rewriting. (pdf)
Andrew Hilton and Amir Roth
ISCA-34, June 2007.

Serialization-Aware Mini-Graphs: Performance with Fewer Resources. (pdf)
Anne Bracy and Amir Roth
MICRO-39, December 2006.

NoSQ: Store-Load Communication without a Store Queue. (pdf)
Tingting Sha, Milo M.K. Martin, and Amir Roth
MICRO-39, December 2006.

Subleties of Transactional Memory Atomicity Semantics. (pdf)
Colin Blundell, E Christopher Lewis, and Milo M. K. Martin
Computer Architecture Letters, Volume 5, Number 2, November 2006.

Store Vulnerability Window (SVW): A Filter and Potential Replacement for Load Re-Execution. (pdf)
Amir Roth
JILP, Vol. 8, September 2006.

This page last modified Wednesday, 07-Mar-2012 18:47:57 EST